adsp-21483 Analog Devices, Inc., adsp-21483 Datasheet - Page 39

• Manufacturer Part Number: adsp-21483
• Description: Sharc Processor
• Manufacturer: Analog Devices, Inc.

Preliminary Technical Data
Input Data Port (IDP)
The timing requirements for the IDP are given in
signals are routed to the DAI_P20–1 pins using the SRU. There-
fore, the timing specifications provided below are valid at the
DAI_P20–1 pins.
Table 34. Input Data Port (IDP)
1
Parameter
Timing Requirements
t
t
t
t
t
t
The serial clock, data and frame sync signals can come from any of the DAI pins. The serial clock and frame sync signals can also come via PCG or SPORTs. PCG's input can
SISFS
SIHFS
SISD
SIHD
IDPCLKW
IDPCLK
be either CLKIN or any of the DAI pins.
1
1
1
1
Frame Sync Setup Before Serial Clock Rising Edge
Frame Sync Hold After Serial Clock Rising Edge
Data Setup Before Serial Clock Rising Edge
Data Hold After Serial Clock Rising Edge
Clock Width
Clock Period
(SERIAL CLOCK)
(FRAME SYNC)
DAI_P20–1
DAI_P20–1
DAI_P20–1
(DATA)
Table
Rev. PrA | Page 39 of 66 | March 2010
Figure 25. IDP Master Timing
t
34. IDP
IPDCLKW
t
SISFS
SAMPLE EDGE
t
SISD
ADSP-21483/21486/21487/21488/21489
t
t
SIHFS
SIHD
t
IPDCLK
Min
4
2.5
2.5
2.5
(t
t
PCLK
PCLK
× 4
× 4) ÷ 2 – 1
Max
Unit
ns
ns
ns
ns
ns
ns