adsp-21483 Analog Devices, Inc., adsp-21483 Datasheet - Page 6

• Manufacturer Part Number: adsp-21483
• Description: Sharc Processor
• Manufacturer: Analog Devices, Inc.

ADSP-21483/21486/21487/21488/21489
Flexible Instruction Set
The 48-bit instruction word accommodates a variety of parallel
operations, for concise programming. For example, the
ADSP-2148x can conditionally execute a multiply, an add, and a
subtract in both processing elements while branching and fetch-
ing up to four 32-bit values from memory, all in a single
instruction.
Variable Instruction Set Architecture (VISA)
In addition to supporting the standard 48-bit instructions from
previous SHARC processors, the ADSP-2148x supports new
instructions of 16 and 32 bits. This feature, called Variable
Instruction Set Architecture (VISA), drops redundant/unused
bits within the 48-bit instruction to create more efficient and
compact code. The program sequencer supports fetching these
16-bit and 32-bit instructions from both internal and external
SDRAM memory. This support is not extended to the
asynchronous memory interface (AMI). Source modules need
to be built using the VISA option, in order to allow code genera-
tion tools to create these more efficient opcodes.
On-Chip Memory
The ADSP-21483 and the ADSP-21488 processors contain 3
Mbits of internal RAM
ADSP-21487, and ADSP-21489 processors contain 5 Mbits of
internal RAM
cycle, independent accesses by the core processor and I/O pro-
ROM Based Security
The ADSP-2148x has a ROM security feature that provides
hardware support for securing user software code by preventing
unauthorized reading from the internal code when enabled.
When using this feature, the processor does not boot-load any
external code, executing exclusively from internal ROM. Addi-
tionally, the processor is not freely accessible via the JTAG port.
Instead, a unique 64-bit key, which must be scanned in through
the JTAG or Test Access Port will be assigned to each customer.
The device will ignore a wrong key. Emulation features and
external boot modes are only available after the correct key is
scanned.
Digital Transmission Content Protection
The DTCP specification defines a cryptographic protocol for
protecting audio entertainment content from illegal copying,
intercepting, and tampering as it traverses high performance
digital buses, such as the IEEE 1394 standard. Only legitimate
entertainment content delivered to a source device via another
approved copy protection system (such as the DVD content
scrambling system) is protected by this copy protection system.
For more information on this feature, contact your local ADI
sales office.
On-Chip Memory Bandwidth
The internal memory architecture allows programs to have four
accesses at the same time to any of the four blocks (assuming
there are no block conflicts). The total bandwidth is realized
using the DMD and PMD buses (2 x 64-bits, CCLK speed) and
the IOD0/1 buses (2 x 32-bit, PCLK speed).
(Table
4). Each memory block supports single-
(Table
3) and the ADSP-21486,
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cessor. The ADSP-2148x memory architecture, in combination
with its separate on-chip buses, allow two data transfers from
the core and one from the I/O processor, in a single cycle.
The processor’s SRAM can be configured as a maximum of
160k words of 32-bit data, 320k words of 16-bit data, 106.7k
words of 48-bit instructions (or 40-bit data), or combinations of
different word sizes up to 5 megabits. All of the memory can be
accessed as 16-bit, 32-bit, 48-bit, or 64-bit words. A 16-bit
floating-point storage format is supported that effectively dou-
bles the amount of data that may be stored on-chip. Conversion
between the 32-bit floating-point and 16-bit floating-point
formats is performed in a single instruction. While each mem-
ory block can store combinations of code and data, accesses are
most efficient when one block stores data using the DM bus for
transfers, and the other block stores instructions and data using
the PM bus for transfers.
Using the DM bus and PM buses, with one bus dedicated to a
memory block, assures single-cycle execution with two data
transfers. In this case, the instruction must be available in the
cache.
The memory maps in
internal memory address space of the processors. The 48-bit
space section describes what this address range looks like to an
instruction that retrieves 48-bit memory. The 32-bit section
describes what this address range looks like to an instruction
that retrieves 32-bit memory.
FAMILY PERIPHERAL ARCHITECTURE
The ADSP-2148x family contains a rich set of peripherals that
support a wide variety of applications including high quality
audio, medical imaging, communications, military, test equip-
ment, 3D graphics, speech recognition, motor control, imaging,
and other applications.
External Port
The external port is available in the 176-lead LQFP package. The
external port interface supports access to the external memory
through core and DMA accesses. The external memory address
space is divided into four banks. Any bank can be programmed
as either asynchronous or synchronous memory. The external
ports are comprised of the following modules.
• An Asynchronous Memory Interface which communicates
• An SDRAM controller that supports a glueless interface
• Arbitration logic to coordinate core and DMA transfers
with SRAM, FLASH, and other devices that meet the stan-
dard asynchronous SRAM access protocol. The AMI
supports 14M words of external memory in bank 0 and
16M words of external memory in bank 1, bank 2, and
bank 3.
with any of the standard SDRAMs. The SDC supports 62M
words of external memory in bank 0, and 64M words of
external memory in bank 1, bank 2, and bank 3.
between internal and external memory over the external
port.
Preliminary Technical Data
Table 3
and
Table 4 on Page 8
displays the