adsp-21483 Analog Devices, Inc., adsp-21483 Datasheet - Page 20

• Manufacturer Part Number: adsp-21483
• Description: Sharc Processor
• Manufacturer: Analog Devices, Inc.

ADSP-21483/21486/21487/21488/21489
PACKAGE INFORMATION
The information presented in
the package branding for the ADSP-2148x processors. For a
complete listing of product availability, see
Page
Table 11. Package Brand Information
1
ESD SENSITIVITY
MAXIMUM POWER DISSIPATION
See Engineer-to-Engineer Note “Estimating Power Dissipation
for ADSP-2148x SHARC Processors” for detailed thermal and
power information regarding maximum power dissipation. For
information on package thermal specifications, see
Characteristics on Page
Brand Key
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Non Automotive only. For branding information specific to Automotive
products, contact Analog Devices Inc.
65.
ESD (electrostatic discharge) sensitive device.
Charged devices and circuit boards can discharge
without detection. Although this product features
patented or proprietary protection circuitry, damage
may occur on devices subjected to high energy ESD.
Therefore, proper ESD precautions should be taken to
avoid performance degradation or loss of functionality.
Figure 3. Typical Package Brand
#yyww country_of_origin
57.
Field Description
Temperature Range
Package Type
RoHS Compliant Option
See Ordering Guide
Assembly Lot Code
Silicon Revision
RoHS Compliant Designation
Date Code
ADSP-2148x
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provides details about
1
Ordering Guide on
Rev. PrA | Page 20 of 66 | March 2010
Thermal
ABSOLUTE MAXIMUM RATINGS
Stresses greater than those listed in
nent damage to the device. These are stress ratings only;
functional operation of the device at these or any other condi-
tions greater than those indicated in the operational sections of
this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device
reliability.
Table 12. Absolute Maximum Ratings
TIMING SPECIFICATIONS
Use the exact timing information given. Do not attempt to
derive parameters from the addition or subtraction of others.
While addition or subtraction would yield meaningful results
for an individual device, the values given in this data sheet
reflect statistical variations and worst cases. Consequently, it is
not meaningful to add parameters to derive longer times. See
Figure 45 on page 56
ence levels.
Switching Characteristics specify how the processor changes its
signals. Circuitry external to the processor must be designed for
compatibility with these signal characteristics. Switching char-
acteristics describe what the processor will do in a given
circumstance. Use switching characteristics to ensure that any
timing requirement of a device connected to the processor (such
as memory) is satisfied.
Timing Requirements apply to signals that are controlled by cir-
cuitry external to the processor, such as the data input for a read
operation. Timing requirements guarantee that the processor
operates correctly with other devices.
Core Clock Requirements
The processor’s internal clock (a multiple of CLKIN) provides
the clock signal for timing internal memory, the processor core,
and the serial ports. During reset, program the ratio between the
processor’s internal clock frequency and external (CLKIN)
clock frequency with the CLK_CFG1–0 pins.
The processor’s internal clock switches at higher frequencies
than the system input clock (CLKIN). To generate the internal
clock, the processor uses an internal phase-locked loop (PLL,
see
between the system clock (CLKIN) signal and the processor’s
internal clock.
Parameter
Internal (Core) Supply Voltage (V
External (I/O) Supply Voltage (V
Thermal Diode Supply Voltage (V
Input Voltage
Output Voltage Swing
Storage Temperature Range
Junction Temperature While Biased
Figure
4). This PLL-based clocking minimizes the skew
Preliminary Technical Data
under
Test Conditions
DD
DD
DD
_
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_
_
Table 12
INT
THD
)
)
) –0.3 V to +4.6 V
Rating
–0.3 V to +1.32 V
–0.3 V to +4.6 V
–0.5 V to +3.8 V
–0.5 V to V
–65°C to +150°C
125°C
may cause perma-
for voltage refer-
DD
_
EXT
+0.5 V