mc68hc908jb8 Freescale Semiconductor, Inc, mc68hc908jb8 Datasheet - Page 112

• Manufacturer Part Number: mc68hc908jb8
• Description: M68hc08 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

System Integration Module (SIM)
8.7.2 Stop Mode
Technical Data
112
NOTE:
NOTE:
In stop mode, the SIM counter is reset and the system clocks are
disabled. An interrupt request from a module can cause an exit from stop
mode. Stacking for interrupts begins after the selected stop recovery
time has elapsed. Reset or break also causes an exit from stop mode.
The SIM disables the oscillator signals (OSCOUT and OSCXCLK) in
stop mode, stopping the CPU and peripherals. Stop recovery time is
selectable using the SSREC bit in the configuration register (CONFIG).
If SSREC is set, stop recovery is reduced from the normal delay of 4096
OSCXCLK cycles down to 2048. This is ideal for applications using
canned oscillators that do not require long startup times from stop mode.
External crystal applications should use the full stop recovery time by
clearing the SSREC bit.
A break interrupt during stop mode sets the SIM break stop/wait bit
(SBSW) in the break status register (BSR).
The SIM counter is held in reset from the execution of the STOP
instruction until the beginning of stop recovery. It is then used to time the
recovery period.
To minimize stop current, all pins configured as inputs should be driven
to a logic 1 or logic 0.
CPUSTOP
NOTE: Previous data can be operand data or the STOP opcode, depending on the last
R/W
IAB
IDB
instruction.
System Integration Module (SIM)
STOP ADDR
Figure 8-16. Stop Mode Entry Timing
Figure 8-16
PREVIOUS DATA
MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3
STOP ADDR + 1
shows stop mode entry timing.
NEXT OPCODE
SAME
Freescale Semiconductor
SAME
SAME
SAME