mc68hc908jb8 Freescale Semiconductor, Inc, mc68hc908jb8 Datasheet - Page 241

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mc68hc908jb8

Manufacturer Part Number
mc68hc908jb8
Description
M68hc08 Microcontrollers
Manufacturer
Freescale Semiconductor, Inc
Datasheet

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15.5 COP Control Register
15.6 Interrupts
15.7 Monitor Mode
MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3
Freescale Semiconductor
Address:
Reset:
COPRS — COP Rate Select Bit
COPD — COP Disable Bit
The COP control register is located at address $FFFF and overlaps the
reset vector. Writing any value to $FFFF clears the COP counter and
starts a new timeout period. Reading location $FFFF returns the low
byte of the reset vector.
The COP does not generate CPU interrupt requests.
The COP is disabled in monitor mode when V
IRQ pin or on the RST pin.
Read:
Write:
COPRS selects the COP timeout period. Reset clears COPRS.
COPD disables the COP module.
1 = COP timeout period is (2
0 = COP timeout period is (2
1 = COP module disabled
0 = COP module enabled
$FFFF
Bit 7
Computer Operating Properly (COP)
Figure 15-3. COP Control Register (COPCTL)
6
5
Low byte of reset vector
Clear COP counter
Unaffected by reset
4
13
18
– 2
– 2
4
4
Computer Operating Properly (COP)
)
)
3
OSCXOUT cycles
OSCXOUT cycles
DD
+ V
2
HI
COP Control Register
is present on the
1
Technical Data
Bit 0
241

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