mc68hc908jb8 Freescale Semiconductor, Inc, mc68hc908jb8 Datasheet - Page 238

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mc68hc908jb8

Manufacturer Part Number
mc68hc908jb8
Description
M68hc08 Microcontrollers
Manufacturer
Freescale Semiconductor, Inc
Datasheet

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Computer Operating Properly (COP)
15.3 Functional Description
Technical Data
238
NOTE:
1. See SIM section for more details.
INTERNAL RESET SOURCES
(COPRS FROM CONFIG)
RESET VECTOR FETCH
COPD (FROM CONFIG)
COPEN (FROM SIM)
COPCTL WRITE
COPCTL WRITE
COP RATE SEL
OSCXCLK
RESET
Figure 15-1
The COP counter is a free-running 6-bit counter preceded by a 12-bit
system integration module (SIM) counter. If not cleared by software, the
COP counter overflows and generates an asynchronous reset after
2
COP rate select bit, COPRS in the configuration register. With a 2
OSCXCLK cycle overflow option (COPRS = 0), a 12MHz OSCXCLK
clock (6MHz crystal) gives a COP timeout period of 21.84 ms. Writing
any value to location $FFFF before an overflow occurs prevents a COP
reset by clearing the COP counter and stages 12 through 5 of the SIM
counter.
(1)
18
– 2
Figure 15-1. COP Block Diagram
4
or 2
Computer Operating Properly (COP)
COP MODULE
COP CLOCK
12-BIT SIM COUNTER
13
shows the structure of the COP module.
– 2
COP COUNTER
4
6-BIT COP COUNTER
CLEAR
OSCXCLK cycles, depending on the state of the
MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3
SIM
RESET STATUS REGISTER
SIM RESET CIRCUIT
Freescale Semiconductor
18
– 2
4

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