dp83261 National Semiconductor Corporation, dp83261 Datasheet
dp83261
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dp83261 Summary of contents
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... DP83261 BMAC TM Device (FDDI Media Access Controller) General Description The DP83261 BMAC device implements the Media Access Control (MAC) protocol for operation in an FDDI token ring The BMAC device provides a flexible interface to the BSI-2 device The BMAC device offers the capabilities ...
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FDDI CHIP SET OVERVIEW 2 0 ARCHITECTURAL DESCRIPTION 2 1 Ring Engine 2 2 Interfaces 3 0 FEATURE OVERVIEW 4 0 FDDI MAC FACILITIES 4 1 Symbol Set 4 2 Protocol Data Units 4 3 Frame Counts 4 ...
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... DP83257 contains PHY Data request and PHY Data indicate port required for concentrators and dual attach stations DP83261 BMAC Media Access Controller The BMAC device implements the Timed Token Media Ac- cess Control protocol defined by the ANSI X3T9 5 FDDI a TM ...
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Architectural Description The BMAC device receivers transmits and strips or repeats Protocol Data Units (PDUs i e Tokens and Frames) and handles the token management functions required by the timed token protocol in accordance with the FDDI MAC ...
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Architectural Description 2 1 RING ENGINE The BMAC device is operated by the Ring Engine which is comprised of four blocks Receiver Transmitter MAC Pa- rameter RAM and Counters Timers as shown in Figure 2 ...
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Architectural Description The Receiver uses these parameters to compare addresses in incoming frames with its addresses stored in the Parame- ter RAM The Transmitter uses the Parameter RAM for generating the Source Address for all frames (except when ...
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Feature Overview (Continued FDDI MAC SUPPORT The BMAC device implements the Standard ANSI X3T9 5 FDDI MAC protocol for transmitting receiving repeating and stripping frames Many of the capabilities defined in MAC-2 are included in the ...
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FDDI MAC Facilities 4 1 SYMBOL SET The Ring Engine recognizes and generates a set of sym- bols These symbols are used to convey Line States (such as the Idle Line State) Control Sequences (such as the Starting ...
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FDDI MAC Facilities (Continued PDU Fields Start of Frame Sequence The Start of Frame Sequence (SFS) consists of the Pream- ble (PA) followed by the Starting Delimiter (SD) The Preamble is a sequence of zero ...
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FDDI MAC Facilities (Continued) The Source Address has the same length as the Destination Address ( the 16-bit Address the 16-bit Address if the 48-bit Address the ...
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FDDI MAC Facilities (Continued) Frames Generated Externally The Ring Engine transmits frames passed to it from the Sys- tem Interface The data portion of the frame is created by the System Interface This begins with the FC field ...
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FDDI MAC Facilities (Continued) Beacon Frames Beacon frames are transmitted continuously with minimum preamble when the Ring Engine is in the Transmit Beacon state The format of Beacon frames generated by the Ring Engine is shown in Table ...
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FDDI MAC Facilities (Continued Token Holding Timer The Token Holding timer (THT) is used to limit the amount of ring bandwidth used by a station for asynchronous traffic once the token is captured THT is ...
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FDDI MAC Facilities (Continued Restricted Asynchronous Service Class The Restricted Asynchronous service class is useful for large transfers requiring all of the available Asynchronous bandwidth The Restricted Token service is useful for large transfers requiring ...
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Functional Description If TRT expires while Late Flag is set TRT is loaded with TMAX and the recovery process (Claim) is invoked When TRT expires and the ring is not operational TRT is loaded with TMAX TRT is ...
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Functional Description In addition to the criteria mentioned above additional crite- ria apply to the servicing of Synchronous and Restricted Requests Synchronous Requests are not serviced if RELR BCNR is set (See Section ...
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Functional Description RQRCLS Name 0000 None Async 0001 Apri 1 THSH1 0010 Reserved Reserved 0011 Reserved Reserved 0100 Syn Synch 0101 Imm Immediate 0110 ImmN Immediate 0111 ImmR Immediate 1000 Asyn Asynch 1001 Rbeg Restricted 1010 Rend Restricted ...
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Functional Description SA Transparency also overrides the Long and Short Ad- dressing enables For example if Long Addressing is not enabled it is still possible to transmit frames with Long Ad- dresses Similarly if Short Addressing is not ...
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Functional Description 5 5 FRAME STATUS PROCESSING Each frame contains three or more Control Indicators The FDDI Standard specifies three the E A and C Indicators When a frame is transmitted the Control Indicators are transmitted as R ...
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Functional Description Odd Symbols Handling When the first T symbol of a frame is received as the sec- ond symbol of a symbol pair (the T symbol is received off- boundary) the Ring Engine corrects ...
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Functional Description Beacon Process Receive When a Beacon frame is received its Frame Type is report- ed (Beacon frame) along with the type of Beacon frame There are two types of Beacon frames My Beacon ...
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Functional Description by setting bit Function BCN to One Entry to the Claim State can be forced by setting bit Function CLM to One While in the Claim or Beacon state the Ring Engine will transmit internally generated ...
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Control Information The Control Information includes Operation Event Status and Parameter Registers that are used to manage and op- erate the Ring Engine A processor on the external Control Bus gains access to read and write these parameters ...
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Control Information (Continued) Addr Name CMP 9 – B Reserved RES RES C CRS0 RFLG RS2 D Reserved RES RES E CTS0 ROP TS2 F Reserved RES RES 10 RELR0 RES DUP ADD DUP 11 ...
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Control Information (Continued) TABLE 6-4 MAC Parameter RAM Address Name Contents 40 MLA0 MLA(47 – 40) 41 MLA1 MLA(39 – 32) 42 MLA2 MLA(31 – 24) 43 MLA3 MLA(23-16) 44 MLA4 MLA(15 – MLA5 MLA(7 – ...
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Control Information (Continued) TABLE 6-5 MAC Counters and Timer Thresholds Address Name Contents 80 – 86 Reserved 87 THSH1 Null(7 – 4) THSH1(3 – – 92 Reserved 93 TMAX Null(7 – 4) TMAX(3 – ...
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Control Information (Continued) Mode Register (Mode) The Mode Register (Mode) contains the current mode of the BMAC device ACCESS RULES Address Read 00h Always REGISTER BITS DIAG ILB RES RES Bit Symbol D0 RUN ...
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Control Information (Continued) Option Register (Option) The Ring Engine supports several options These options are typically static during operation but may be altered during operation This register is initialized to Zero after a master reset ACCESS RULES Address ...
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Control Information (Continued) Option Register (Continued) Bit Symbol D4 IRPT Inhibit Repeat When enabled 1 the Ring Engine cannot enter the Transmitter Repeat and Issue Token states This causes all received PDUs to be stripped and prevents tokens ...
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Control Information (Continued) Function Register (Function) The Ring Engine performs the MAC Reset Claim Request and Beacon Request using the Function Register The Register is initialized to Zero after a master reset A function is performed by setting ...
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Control Information (Continued) Revision Register (Rev) The Revision Register (Rev) contains the revision number of the BMAC device ACCESS RULES Address Read 07h Always Data Ignored REGISTER BITS REV7 REV6 REV5 REV4 Bit Symbol ...
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Control Information (Continued EVENT REGISTERS The Event Registers record the occurrence of events or series of events Events are recorded and contribute to gen- erating the Interrupt signal There is a two-level hierarchy in generating this ...
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Control Information (Continued) Compare Register (CMP) The Compare Register (CMP) is written with the contents of a conditional event latch registers when it is read The Compare Register may also be written to directly During a write to ...
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Control Information (Continued) Current Receiver Status Register (CRS0) The Current Receiver Status Register (CRS0) records the status of the Receiver state machine It is continuously updated It remains stable when accessed When in Diagnose Mode this register is ...
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Control Information (Continued) Current Transmitter Status Register (CTS0) The Current Transmitter Status Register (CTS0) records the status of the Transmitter state machine It is continuously updated It remains stable when accessed When in Diagnose Mode this register is ...
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Control Information (Continued) Ring Event Latch Register (RELR0) The Ring Event Latch Register 0 (RELR0) captures conditions that occur on the Ring including the receipt of Beacon and Claim frames transitions in the Ring Operational flag and the ...
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Control Information (Continued) Ring Event Mask Register 0 (REMR0) The Ring Event Mask Register 0 (REMR0) is used to mask bits in Register RELR0 If a bit in Register REMR0 is set to One the corresponding bit in ...
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Control Information (Continued) Ring Event Latch Register 1 (RELR1) The Ring Event Latch Register 1 (RELR1) captures the progress of the Beacon and Claim Processes During the Beacon Process it records reception of an Other Beacon or a ...
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Control Information (Continued) Ring Event Mask Register 1 (REMR1) The Ring Event Mask Register 1 (REMR1) is used to mask bits in Register RELR1 If a bit in Register REMR1 is set to One the corresponding bit in ...
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Control Information (Continued) Token and Timer Event Latch Register 0 (TELR0) The Token and Timer Event Latch Register 0 (TELR0) informs software of expirations of the Token Rotation Timer (TRT) and Valid Transmission Timer (TVX) The TELR0 Register ...
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Control Information (Continued) Token and Timer Event Mask Register 0 (TEMR0) The Token and Timer Event Mask Register 0 (TEMR0) is used to mask bits in Register TELR0 If a bit in Register TEMR0 is set to One ...
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Control Information (Continued) Counter Increment Latch Register (CILR) The Counter Increment Latch Register (CILR) records the occurrence of any increment to the Event Counters Each bit corresponds to a counter and is set when the corresponding counter is ...
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Control Information (Continued) Counter Increment Mask Register (CIMR) The Counter Increment Mask Register (CIMR) is used to mask bits from the Counter Increment Latch Register (CILR bit in Register CIMR is set to One the corresponding ...
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Control Information (Continued) Counter Overflow Latch Register (COLR) The Counter Overflow Latch Register (COLR) records carry events from the 20th bit of the Event Counters Each bit in the COLR corresponds to an individual counter Each bit may ...
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Control Information (Continued) Counter Overflow Mask Register (COMR) The Counter Overflow Mask Register (COMR) is used to mask bits from the Counter Overflow Latch Register (COLR bit in Register COMR is set to One the corresponding ...
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Control Information (Continued) Internal Event Latch Register (IELR) The Internal Event Latch Register (IELR) reports internal errors in the BMAC device These errors include MAC Parity errors and inconsistencies in the Receiver and Transmitter state machines After an ...
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Control Information (Continued) Exception Status Register (ESR) The Exception Status Register (ESR) reports errors to the software Errors include PHY Interface Parity errors illegal attempts to access currently inaccessible registers and writing to a conditional write location if ...
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Control Information (Continued) Exception Mask Register (EMR) The Exception Mask Register (EMR) is used to mask bits in the Exception Status Register (ESR bit in Register EMR is set to One the corresponding bit in Register ...
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Control Information (Continued) Interrupt Condition Register (ICR) The Interrupt Condition Register (ICR) collects unmasked interrupts from the Event Registers Interrupts are categorized into Ring Events Token and Timer Events Counter Events and Error and Exceptional Status Events If ...
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Control Information (Continued) Interrupt Mask Register (IMR) The Interrupt Mask Register (IMR) is used to mask bits in the Interrupt Condition Register (ICR bit in Register IMR and the corresponding bit in Register ICR are set ...
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Control Information (Continued MAC PARAMETERS The MAC Parameters are accessible in the Stop Mode These parameters are also accessible in the Run Mode when the following conditions are met a) the MAC Transmitter is in state ...
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Control Information (Continued Group Addresses The Ring Engine supports detection of Group Addresses within programmable and fixed blocks of consecutive addresses The algorithm used by the Ring Engine first performs a comparison between the most ...
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Control Information (Continued) Group Short Address Group Short Address (GSA0) represents the station’s short 16-bit address bit GSA(15) to bit GSA( possible to disable Short Group Addressing by programming bits GSA(14 – all Ones ...
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Control Information (Continued) Programmable Group Address MAP (PGM0 – PGM1F) If the first 40 bits of a long DA DA(47 – 8) match the GLA or if the first 8 bits of a short DA DA(15 – 8) ...
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Control Information (Continued) Programmable Group Address MAP (PGM0 – PGM1F) (Continued) ACCESS RULES Address Read 60 – 6Fh Stop Mode Stop Mode D7 D6 PGM10 PGM(87) PGM(86) PGM11 PGM(8F) PGM(8E) PGM12 PGM(97) PGM(96) PGM13 PGM(9F) PGM(9E) PGM14 PGM(A7) ...
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Control Information (Continued Claim Information Requested Target Token Rotation Time (TREQ) The Requested Target Token Rotation Time (TREQ) is stored in registers TREQ0 – TREQ3 TREQ(31 – represented as a negative two’s complement ...
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Control Information (Continued TIMER VALUES The Ring Engine stores several timer values and thresholds used in normal operation With the exception of TNEG the timers use an exponential expansion on a 4-bit value to produce a ...
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Control Information (Continued) Maximum Token Rotation Time (TMAX) The Maximum Token Rotation Time (TMAX) denotes the maximum Target Token Rotation Time supported by this station TMAX is stored as a 4-bit value that is expanded to a binary ...
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Control Information (Continued) Valid Transmission Time (TVX) The Valid Transmission Timer (TVX) is used to increase the responsiveness of the ring to errors that cause ring recovery The TVX value denotes the maximum time in which a valid ...
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Control Information (Continued) Negotiated Target Rotation Time (TNEG) The Negotiated Target Rotation Time (TNEG0 – 32-bit twos complement value It is the result of the Claim Process TNEG is loaded either directly from the received ...
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Control Information (Continued EVENT COUNTERS The Event Counters are used to gain access to the internal 20-bit counters used to gather statistics The following event counters are included Frame Received Counter (FRCT1– Error ...
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Control Information (Continued) Frame Received Counter (FRCT) The Frame Received Counter (FRCT) is specified in the FDDI MAC Standard It is the count of all complete frames received including MAC frames Void frames and frames stripped by this ...
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Control Information (Continued) Error Isolated Counter (EICT) The Error Isolated Counter (EICT) is specified in the FDDI MAC Standard It is the count of all error frames detected by this station and no previous station It is incremented ...
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Control Information (Continued) Lost Frame Counter (LFCT) The Lost Frame Counter (LFCT) is specified in the FDDI MAC Standard It is the count of all instances where a Format Error is detected in a frame or token such ...
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Control Information (Continued) Frame Copied Counter (FCCT) The Frame Copied Counter (FCCT) maintains the count of the number of frames successfully copied by this station This counter can be used to accumulate station performance statistics The Frame Copied ...
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Control Information (Continued) Frame Not Copied Counter (FNCT) The Frame Not Copied Counter (FNCT) maintains a count of the number of frames intended for this station that were not successfully copied by this station This count can be ...
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Control Information (Continued) Frame Transmitted Counter (FTCT) The Frame Transmitted Counter (FTCT) maintains the count of frames transmitted successfully by this station The counter can be used to accumulate station performance statistics The Frame Transmitted Counter is incremented ...
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Control Information (Continued) Token Received Counter (TKCT) The Token Received Counter (TKCT) maintains the count of valid tokens received by this station The counter can be used with the Ring Latency Counter to calculate the average network load ...
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Control Information (Continued) Ring Latency Counter (RLCT) The Ring Latency Counter (RLCT measurement of time for PDUs to propagate around the ring This counter contains the last measured ring latency whenever the RLVD bit of the ...
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Control Information (Continued) Late Count (LTCT) The Late Count Counter (LTCT) is implemented differently than suggested by the FDDI MAC Standard but provides similar information The function of the Late Count Counter is divided between the Late Flag ...
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Signal Descriptions Interface Organization The BMAC device signals are organized into five Interfaces Control Interface Used for processor access to the BMAC device PHY Interface Interface signals to the DP83251 55 PLAYER device MAC Indicate Interface Signals for ...
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Signal Descriptions (Continued PHY INTERFACE The PHY Interface signals transfer symbol pairs between the BMAC and PLAYER devices Transfers are synchronous using the 12 5 MHz Local Byte Clock signal (signal provided by the Clock Distribution ...
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Signal Descriptions (Continued PHY Interface Codes The DP83251 155 PLAYER device converts the Standard 4B 5B FDDI symbol code to the internal code used at the PHY Interface The PH DATA Indication table shows how ...
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Signal Descriptions (Continued) PH DATA Request The Ring Engine generates the 10 bit byte stream as defined in Table 7-2 Note that all symbol pairs are either control or data symbol pairs Mixed data control symbol pairs are ...
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Signal Descriptions (Continued MAC INDICATION INTERFACE The MAC Indication Interface provides a delayed version of the byte stream presented to the Ring Engine at the PHY Indication Interface Every byte of all incoming frames is presented ...
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Signal Descriptions (Continued) Termination Status These signals provide status on reception of a valid ending delimiter on a frame VDL Valid Data Length Criteria 1 more than the minimum number bytes 2 integral number of symbol pairs Valid ...
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Signal Descriptions (Continued Signals All output signals change relative to the rising edge of the Local Byte Clock signal (provided by the Clock Distribution Device) and are active high Indication Data ...
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Signal Descriptions (Continued PDU Sequencing The PDU Sequencing signals apply to the data and status available at the MAC Indicate Interface They are used to determine the validity of the data (MID7 – 0) ...
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Signal Descriptions (Continued PDU Flags The PDU flags may be used with the received Frame Control field to determine if an attempt should be made to copy the frame Symbol Pin I O AFLAG ...
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Signal Descriptions (Continued Termination Event The terminating event for all PDUs is provided in the PDU Status signals When a token is terminated by a valid Ending Delimiter (TT symbol pair) the TKRCVD signal ...
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Signal Descriptions (Continued External Flags The External Flags provide input to the Ring Engine in order to set the A and C indicators or in order to initiate stripping based on external logic Symbol ...
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Signal Descriptions (Continued Timing Examples The following examples show the sequencing of signals at the MAC Indicate Interface for well formed frames for stripped frames and for several special cases The diagrams show the logical ...
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Signal Descriptions (Continued) 83 ...
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Signal Descriptions (Continued) Remnant Reception In these examples the remnants of frames that were stripped by an upstream station are received Examples are shown for frames where the strip point occurred at an upstream station before during and ...
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Signal Descriptions (Continued) 85 ...
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Signal Descriptions (Continued) 86 ...
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Signal Descriptions (Continued) Frame Stripping 87 ...
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Signal Descriptions (Continued) 88 ...
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Signal Descriptions (Continued) Abnormal Termination Conditions 89 ...
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Signal Descriptions (Continued) MAC Reset can be asserted at any time When MODE0 RUN e 0 MACRST is asserted and remains asserted FIGURE 7-10 MAC Reset 10387 – 17 ...
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Signal Descriptions (Continued MAC REQUEST INTERFACE The MAC Request Interface is used to gain access to the ring and to transmit data into the ring After a Request is submitted to the interface the Ring Engine ...
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Signal Descriptions (Continued) Handshake The Handshake signals control the Request Interface handshaking process They are used for token capture and transmission of PDUs Symbol Pin I O TXPASS 28 O Transmit Pass Indicates the absence of a Service ...
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Signal Descriptions (Continued) Service Parameters The Service Parameters define the Service Request They must be valid for at least one byte time before the RQRDY signal is asserted and must not change while RDRDY remains asserted See Section ...
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Signal Descriptions (Continued) Transmission Status Symbol Pin I O TXED 31 O Transmitted Ending Delimiter Indicates that the Transmitter completed transmission of the current or previous PDU TXED is asserted when the current PHY Request byte is a ...
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Signal Descriptions (Continued Operation The MAC Request Interface has three logical states as determined by TXRDY and TXPASS The interface state machine is shown in Figure 7-11 followed by a description of the conditions states ...
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Signal Descriptions (Continued) State Descriptions MR0 Not Ready In this state the Ring Engine does not have a Service Op- portunity If RQRCLS is not zero the Ring Engine is trying to secure a Service Opportunity meeting the ...
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Signal Descriptions (Continued) SUBSTATE MRR0 Preamble Upon entry to MR1 8 bytes of Preamble (Idles) are transmit- ted in substate MRR0 After the Preamble if a frame can be sent from the inter- face transition MR12 occurs The ...
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Signal Descriptions (Continued Transmission Status Upon leaving MR2 transmission status is available after TXRDY or TXPASS is asserted TXED and TXABORT are normally valid for at least 9 byte times (exception 2 byte times ...
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Signal Descriptions (Continued) 99 ...
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Signal Descriptions (Continued) If RQRCLS remained asserted the token would be held as long as possible and multiple frames could be transmitted this case the TXRDY RQSEND x v RQSEND handshake for the beginning ...
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Signal Descriptions (Continued) 101 ...
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Signal Descriptions (Continued) 102 ...
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Signal Descriptions (Continued) FIGURE 7-16 MAC Reset 103 TL F 10387 – 23 ...
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Signal Descriptions (Continued) FIGURE 7-17 MAC Reset at End of Frame 104 TL F 10387 – 24 ...
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Signal Descriptions (Continued) 105 ...
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Signal Descriptions (Continued) 106 ...
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Signal Descriptions (Continued) 107 ...
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Signal Descriptions (Continued ELECTRICAL INTERFACE The Electrical Interface signals comprise all of the clocking power supply and ground pins Symbol Pin I O LSC 87 I Local Symbol Clock 25 MHz clock with ...
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Signal Descriptions (Continued PINOUT SUMMARY (Continued) TABLE 7-6 Pinout Summary (Continued) Pin Signal Name 20 Request Class 2 21 Request Class 1 22 Request Class 0 23 Request Ready 24 Request Send 25 Request End of ...
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Signal Descriptions (Continued PINOUT SUMMARY (Continued) TABLE 7-6 Pinout Summary (Continued) Pin Signal Name 60 My Source Address Recognized 61 Same Source Address 62 Information Field Received 63 Same MAC Information 64 Ground 65 Positive Power ...
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Signal Descriptions (Continued PINOUT SUMMARY (Continued) TABLE 7-6 Pinout Summary (Continued) Pin Signal Name 100 Positive Power Supply 101 Ground 102 PHY Indicate Data 3 103 PHY Request Data 4 104 PHY Indicate Data 4 105 ...
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... Signal Descriptions (Continued PINOUT DIAGRAM FIGURE 7-21 DP83261 132-Pin PQFP Pinout Order Number DP83261AVF See NS Package Number VF132A 112 TL F 10387 – 11 ...
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Electrical Characteristics 8 1 ABSOLUTE MAXIMUM RATINGS If Military Aerospace specified devices are required please contact the National Semiconductor Sales Office Distributors for availability and specifications Symbol Parameter V Supply Voltage Input Voltage IN V ...
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Electrical Characteristics ELECTRICAL CHARACTERISTICS See Figures 8-8 and 8-9 for AC Signal and TRI-STATE Testing Criteria Control Bus Interface Symbol Parameter T1 CE Setup to LBC T2 LBC Period T3 LBC to ...
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Electrical Characteristics FIGURE 8-1 Control Bus Interface Write Cycle FIGURE 8-2 Control Bus Interface Read Cycle (Continued) 115 TL F 10387 – 10387 – 29 ...
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Electrical Characteristics FIGURE 8-3 Control Bus Interface Synchronous Write Cycle FIGURE 8-4 Control Bus Interface Synchronous Read Cycle (Continued) 116 TL F 10387 – 10387 – 31 ...
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Electrical Characteristics Clock Signals Symbol Parameter T21 LSC to LBC Lead Time (Skew Left) T22 LSC Pulse Width High T23 LSC Pulse Width Low T24 LBC Pulse Width High T25 LBC Pulse Width Low 8 ...
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Electrical Characteristics MAC Interface Pin Groups Group SAIGT SAT STRIP EA VCOPY RQEOF RQSEND RQFINAL 2 I RQRDY 3 I FCST RQBCN RQCLS(3 – RQABT 4 I RQCLM 5 ...
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Electrical Characteristics Test Conditions for AC Testing (ACK INT Signal Testing Note ...
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Electrical Characteristics Test Equivalent Loads V Testing OL2 Tlo-tri Open Drain V Testing OL (Continued 10387 – 10387 – 10387 – 41 FIGURE 8-10 Test Equivalent Loads 120 ...
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Appendix A Ring Engine State Machines A 1 RECEIVER MAC Receiver State Diagram FIGURE A-1 Ring Engine Receiver State Diagram 121 TL F 10387 – 43 ...
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Appendix A Ring Engine State Machines MAC RECEIVER FOOTNOTES Internal Conditions (1) ESA Option Enable Short Address (2) ELA Option Enable Long Address (3) IRR Option Inhibit Recovery Required (4) IFCS Option Implementer FCS ...
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Appendix A Ring Engine State Machines 2 SA Actions IF FCSL 4 0 short address After SA1r SIGNAL SARCVD IF ESA THEN IF SAr 4 MSA THEN SET MFLAG ELSE IF SAr IF ((SAr 4 previous SAr) ( ...
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Appendix A Ring Engine State Machines 5 ED Actions INC FRCT Frame Received Ct SIGNAL FR Received EDRDVD SET CILR FRRCV If Valid Data Length (FCr 4 Implementer and n(Option IFCS)) THEN RESET TVX Flag (EA Option ...
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Appendix A Ring Engine State Machines 6 Ar Actions After THEN CLEAR N Flag IF A Flag THEN SET RELR DUPADD IF REV1 nE Flag (A Flag IF ...
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Appendix A Ring Engine State Machines A 2 TRANSMITTER MAC Transmitter State Diagram FIGURE A-2 Ring Engine Transmitter State Diagram (Continued) 126 TL F 10387 – 44 ...
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Appendix A Ring Engine State Machines MAC TRANSMITTER FOOTNOTES Internal Conditions (1) ESA Option Enable Short Address (2) ELA Option Enable Long Address (3) IRPT l Option Inhibit Repeat (4)ITC Option Inhibit Token ...
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Appendix A Ring Engine State Machines (6) Another Void After FSx TX Pass Void Strip (7) Reset Required l MAC Reset l (nIRPT (Higher Claim Other Beacon l (IRPT (T3 (T0 (Ring Operational Note Any other MAC frame received while ...
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Appendix A Ring Engine State Machines (5) Recovery Actions IF T2 nTX Ready nTX Pass THEN SET TX Abort IF T5 THEN CLEAR TX Abort CLEAR TX Ready TX Ack Void Strip SET TX Class 4 nonrestricted SET T Opr ...
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Appendix A Ring Engine State Machines (4) Repeat Actions (T1) IF nIRPT (Higher Claim l (Ring Operational TX Class THEN SET TX Class 4 none SET T Opr 4 T Max IF Ring Operational THEN SET RELR Ring Operational Reset ...
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... National does not assume any responsibility for use of any circuitry described no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications 132-Pin PQFP Order Number DP83261AVF NS Package Number VF132A 2 A critical component is any component of a life ...