dp83261 National Semiconductor Corporation, dp83261 Datasheet - Page 26

dp83261

Manufacturer Part Number

dp83261

Description

Bmac Device Fddi Media Access Controller

Manufacturer

National Semiconductor Corporation

Datasheet

1.DP83261.pdf (132 pages)

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6 0 Control Information

TABLE 6-5 MAC Counters and Timer Thresholds

Address

9C – 9E

80 – 86

88 – 92

94 – 96

Reserved

TNEG0

TNEG1

TNEG2

TNEG3

THSH1

FRCT0

FRCT1

FRCT2

FRCT3

FCCT0

FCCT1

FCCT2

FCCT3

LFCT0

LFCT1

LFCT2

LFCT3

Name

TMAX

EICT0

EICT1

EICT2

EICT3

LTCT

TVX

(Continued)

TNEG(31 – 24)

TNEG(23 – 16)

FRCT(19 – 16)

FCCT(19 – 16)

LFCT(19 – 16)

THSH1(3 – 0)

TNEG(15 – 8)

Zero(31 – 24)

FRCT(15 – 8)

Zero(31 – 24)

EICT(19 – 16)

Zero(31 – 24)

FCCT(15 – 8)

LFCT(15 – 8)

TMAX(3 – 0)

TNEG(7 – 0)

EICT(15 – 8)

FRCT(7– 0)

FCCT(7 – 0)

LTCT(3 – 0)

LFCT(7 – 0)

EICT(7 – 0)

Null(7 – 4)

Contents

TVX(3– 0)

Note The MAC event counters and timer thresholds are always readable

and are writable in Stop mode

Note Null(7–4) indicates that these bits are forced to zero on reads and are

ignored on writes

Note The value obtained on reads from reserved locations is not specified

The Event Counters are 20-bit counters and are read

through three control accesses In order to guarantee a

consistent snapshot whenever byte 3 of an event counter is

read byte 1 and byte 2 of the counters are loaded into a

holding register Byte 1 and byte 2 may then be read from

the holding register A single holding register is shared by all

of the counters but (for convenience) is accessible at sever-

al places within the address space Consistent readings

across counters can be accomplished using the Counter

Increment Latch Register (CILR)

The Event Counters are not reset as a result of a Master

Reset This may be done by either reading the counters out

and keeping track relative to the initial value read or by

writing a value to all of the counters in stop mode The

counters may be written in any order With some excep-

tions interrupts are available when the counters increment

or wraparound

6 3 OPERATION REGISTERS

The Operation Registers are used to control the operation

of the BMAC device The Operation Registers include the

following registers

Mode Register (Mode)

Option Register (Option)

Function Register (Function)

Revision Register (REV)

TABLE 6-5 MAC Counters and Timer Thresholds

Address

FNCT0

FNCT1

FNCT2

FNCT3

FTCT0

FTCT1

FTCT2

FTCT3

TKCT0

TKCT1

TKCT2

TKCT3

RLCT0

RLCT1

RLCT2

RLCT3

(Continued)

Name

FNCT(19 – 16)

FTCT(19 – 16)

TKCT(19 – 16)

RLCT(19 – 16)

Zero(31 – 24)

FNCT(15 – 8)

Zero(31 – 24)

FTCT(15 – 8)

TKCT(15 – 8)

RLCT(15 – 8)

FNCT(7 – 0)

TKCT(7 – 0)

RLCT(7 – 0)

FTCT(7 – 0)

Contents

Null(7 – 4)

dp83261 National Semiconductor Corporation, dp83261 Datasheet - Page 26

dp83261

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