dp83261 National Semiconductor Corporation, dp83261 Datasheet - Page 3

• Manufacturer Part Number: dp83261
• Description: Bmac Device Fddi Media Access Controller
• Manufacturer: National Semiconductor Corporation

1 0 FDDI Chip Set Overview
National Semiconductor’s DP83200 FDDI chip set consists
of five components as shown in Figure 1-1 For more infor-
mation on the other devices of the chip set consult the
appropriate datasheets and application notes
DP83256 56-AP 57 PLAYER
Device Physical Layer Controller
The PLAYER
(PHY) protocol as defined by the ANSI FDDI PHY X3T9 5
Standard along with all the necessary clock recovery and
clock regeneration functions
Features
In
PHY Data request and PHY Data indicate port required
for concentrators and dual attach stations



















Single chip FDDI Physical Layer (PHY) solution
Integrated Digital Clock Recovery Module provides en-
hanced tracking and greater lock acquisition range
Integrated Clock Generation Module provides all neces-
sary clock signals for an FDDI system from an external
12 5 MHz reference
Alternate PMD Interface (DP83256-AP 57) supports
UTP twisted pair FDDI PMDs with no external clock re-
covery or clock generation functions required
No External Filter Components
Connection Management (CMT) Support (LEM TNE
PC React CF React Auto Scrubbing)
Full on-chip configuration switch
Low Power CMOS-BIPOLAR design using a single 5V
supply
Full duplex operation with through parity
Separate management interface (Control Bus)
Selectable Parity on PHY-MAC Interface and Control Bus
Interface
Two levels of on-chip loopback
4B 5B encoder decoder
Framing logic
Elasticity Buffer Repeat Filter and Smoother
Line state detector generator
Supports single attach stations dual attach stations and
concentrators with no external logic
DP83256 56-AP for SAS DAS single path stations
P83257 for SAS DAS single dual path stations
addition
a
the
device implements the Physical Layer
DP83257
contains
an
a
additional
TM
3
DP83261 BMAC
Media Access Controller
The BMAC device implements the Timed Token Media Ac-
cess Control protocol defined by the ANSI X3T9 5 FDDI
MAC Standard
Features
DP83265A BSI-2 Device
System Interface
The BSI-2 device implements an interface between the
BMAC device and a host system
Features























All of the standard defined ring service options
Full duplex operation with through parity
Supports all FDDI Ring Scheduling Classes (Synchro-
nous Asynchronous etc )
Supports Individual Group Short Long and External
Addressing
Generates Beacon Claim and Void frames internally
Extensive ring and station statistic gathering
Extensions for MAC level bridging
Separate management port that is used to configure and
control operation
Multi-frame streaming interface
Fully software and pin compatible with the original BSI
device
Over 2 kbytes of on-chip FIFO
Operates from 12 5 MHz to 33 MHz synchronously with
host system
Provides Address bit swapping capability
Reduces interface logic for SBus adapters
32-bit wide Address Data path with byte parity
Programmable transfer burst sizes of 4 or 8 32-bit words
Interfaces to DRAMs or directly to system bus
2 Output and 3 Input Channels
Supports Header Info splitting
Bridging support
Programmable Big or Little Endian alignment
Full duplex data path
Receive frame filtering services
TM
Device