dp83261 National Semiconductor Corporation, dp83261 Datasheet - Page 47

• Manufacturer Part Number: dp83261
• Description: Bmac Device Fddi Media Access Controller
• Manufacturer: National Semiconductor Corporation

D0
D1 – 4
D5
D6
D7
6 0 Control Information
Exception Status Register (ESR)
The Exception Status Register (ESR) reports errors to the software Errors include PHY Interface Parity errors illegal attempts
to access currently inaccessible registers and writing to a conditional write location if a register bit has changed since it was last
read Each bit may be masked via the Exception Mask Register (EMR)
ACCESS RULES
REGISTER BITS
Bit
CWI
D7
Address
2Ch
Symbol
PPE
RES
CPE
CCE
CWI
CCE
D6
PHY Interface Parity Error Indicates parity error detected on PID7 – 0 Parity errors are reported when
parity is enabled on the PHY Request Interface (bit PIP of the Mode Register is set)
Reserved
Control Bus Parity Error Indicates a Control Bus Parity Error was detected on the Control Bus Data pins
(CBD7 – 0) during a write operation to a register Parity errors are reported if parity is enabled on the Control
Bus Interface (bit CBP of the Mode Register is set)
Control Bus Command Error Indicates that a Control Bus command was not performed due to an error
i e illegal command or a Control Bus Write Parity error An illegal command is an attempt to access a
currently inaccessible register
Conditional Write Inhibit Indicates that at least one bit of the previous conditional write operation was not
written This bit is set unconditionally after each write to a conditional write register if the value of the
Compare Register is not equal to the value of the register that was accessed for a write before it was
written This may indicate that the accessed register has changed since it was last read
This bit is cleared after a successful conditional write This occurs when the value of the Compare Register
is equal to the value of the register that was accessed for a write before it was written
CWI does not contribute to setting the ESE bit of the Interrupt Condition Register (it is always implicitly
masked)
CPE
D5
Always
Read
RES
D4
(Continued)
Condition
RES
D3
Write
RES
D2
47
RES
D1
Description
PPE
D0