dp83261 National Semiconductor Corporation, dp83261 Datasheet - Page 49

• Manufacturer Part Number: dp83261
• Description: Bmac Device Fddi Media Access Controller
• Manufacturer: National Semiconductor Corporation

D0
D1
D2
D3
D4 – 5
D6
D7
6 0 Control Information
Interrupt Condition Register (ICR)
The Interrupt Condition Register (ICR) collects unmasked interrupts from the Event Registers Interrupts are categorized into
Ring Events Token and Timer Events Counter Events and Error and Exceptional Status Events If the bit in the Interrupt Mask
Register (IMR) and the corresponding bit in the ICR are set to One the INT pin is forced low and thus triggers an interrupt
Note Bits are cleared ONLY by clearing underlying conditions (Mask bit and or Event Bit) in the appropriate Event Register
ACCESS RULES
REGISTER BITS
Bit
ESE
D7
Address
2Eh
Symbol
RNG
TTE
CIE
COE
RES
IERR
ESE
IERR
D6
Ring Event Interrupt Is set if corresponding bits in the Ring Event Latch and Mask Registers are set
Token and Timer Event Interrupt Is set if corresponding bits in the Token and Timer Event Latch and
Mask Registers are set
Counter Increment Event Interrupt Is set if corresponding bits in the Counter Increment Latch and Mask
Registers are set
Counter Overflow Event Interrupt Is set if corresponding bits in the Counter Overflow Latch and Mask
Registers are set
Reserved
Internal Error Interrupt Is set if any bits in the Internal Event Register are set
Exception Status Event Interrupt Is set if corresponding bits in the Exception Status and Mask Registers
are set
Always
RES
Read
D5
RES
D4
(Continued)
Data Ignored
Write
COE
D3
CIE
D2
49
TTE
D1
Description
RNG
D0