dp83261 National Semiconductor Corporation, dp83261 Datasheet - Page 40
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dp83261
Manufacturer Part Number
dp83261
Description
Bmac Device Fddi Media Access Controller
Manufacturer
National Semiconductor Corporation
Datasheet
1.DP83261.pdf
(132 pages)
- Current page: 40 of 132
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Bit
D0
D1
D2
D3
D4
D5
D6
D7
6 0 Control Information
Token and Timer Event Latch Register 0 (TELR0)
The Token and Timer Event Latch Register 0 (TELR0) informs software of expirations of the Token Rotation Timer (TRT) and
Valid Transmission Timer (TVX) The TELR0 Register also reports token events such as duplicate token detection restricted
token reception and general token capture and release The completion of the Ring Latency measurement is also indicated in
the TELR0 Register Each bit may be masked via the Token and Timer Event Mask Register (TEMR0)
ACCESS RULES
REGISTER BITS
RLVD TKPASS TKCAPT CBERR DUPTKR TRTEXP TVXEXP ENTRMD
D7
Address
ENTRMD
TVXEXP
TRTEXP
DUPTKR
CBERR
TKCAPT
TKPASS
RLVD
Symbol
14h
D6
Enter Restricted Mode Indicates that a Restricted Token was received and that the R Flag transitioned
from 0 to 1
TVX Expired Indicates that a valid frame or token was not received in TVX time
TRT Expired Indicates that a valid token was not received within 2 TNEG
Duplicate Token Received Indicates that a valid token was received while the transmitter was in state T2
or T3
Claim and or Beacon Error Indicates that the Claim and or Beacon Process failed because TRT expired
while the Transmitter was in state T4 or T5
Token Captured Indicates that a token has been captured
Token Passed Indicates that a valid token has been passed (without capturing it) or has been issued after a
service opportunity
Ring Latency Valid
0 This bit is set to Zero to request a new latency value from the Ring Engine In Rev 01 and all future
1 This bit is set to One when the Ring Latency measurement is complete
This bit is written unconditionally and is not protected by the Compare Register
D5
Revisions the Ring Latency count is set to zero before each measurement
Always
Read
D4
(Continued)
D3
Condition
Write
D2
40
D1
Description
D0
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