dp83261 National Semiconductor Corporation, dp83261 Datasheet - Page 23

• Manufacturer Part Number: dp83261
• Description: Bmac Device Fddi Media Access Controller
• Manufacturer: National Semiconductor Corporation

Addr
3 – 6
6 0 Control Information
The Control Information includes Operation Event Status
and Parameter Registers that are used to manage and op-
erate the Ring Engine A processor on the external Control
Bus gains access to read and write these parameters via
the Control Interface
The Control Information Address Space is divided into 4
groups as shown in Table 6-1 An information summary is
given for each group (see Tables 6-2 through 6-5) followed
by a detailed description of all registers
6 1 CONVENTIONS
When referring to multi-byte fields byte 0 is always the most
significant byte When referring to bits within a byte bit (7) is
the most significant bit and bit (0) is the least significant bit
When referring to the contents of a byte the most signficant
bit is always referred to first
When referring to a bit within a byte the notation
register name bit name is used For example Mode RUN
references the RUN bit in the Mode Register
Note 1 An attempt to access a currently inaccessible location because of the current mode or because it is in a reserved address space will cause a command
error (bit CCE of the Exception Status Register is set to One)
Note 2 Read and write accesses to reserved location within the Operation and Event Address ranges cause a command error (bit CCE of the Exception Status
Register is set to One)
Note 3 The MAC Parameter RAM is also accessible when conditions a b and c are true Otherwise accesses will cause a command error (ESR CEE set to One)
and the access will not be performed
Note Attempts to access reserved locations will result in Command Rejects (ESR CCE set to ONE)
0
1
2
7
a The MAC Transmitter is in states T0 T1 or T3
b Bits ITC and IRR of the Option Register are set to One
c Bits CLM and BCN of the Function Register are not set to One
Address Range
C0 – FF
08 – 2F
30 – 3F
40 – 7F
80 – BF
00 – 07
Reserved
Function
Revision
Option
Name
Mode
DIAG
RES
RES
ITC
D7
EMIND
Operation Registers
RES
RES
MAC Parameters
Counters Timers
ILB
D6
Event Registers
Description
TABLE 6-1 Control Information Address Space
Reserved
Reserved
IFCS
RES
RES
RES
TABLE 6-2 Operation Registers
D5
IRPT
RES
CLM
RES
D4
REV(7 – 0)
23
BCN
RES
IRR
PIP
D3
6 2 ACCESS RULES
All parameters are accessible in Diagnose Mode Reserved
address space is not accessible in any mode Certain Status
and Parameter Registers are not accessible while in Run
mode
All Control Interface accesses are checked against the cur-
rent operational mode to determine if the register is current-
ly accessible If not currently accessible the Control Bus
Interface access is rejected (and reported in an Event Reg-
ister) This means that all Control Bus Interface accesses
complete in a deterministic amount of time
The Exceptional Status Register can be checked to verify
that the operation terminated normally
Read Conditions
Always (Note 2)
Always (Note 2)
(Notes 1 3)
Stop Mode
Always
MCRST
N A
N A
MRP
RES
ITR
D2
CBP
RES
RES
ELA
D1
MARST
RUN
ESA
RES
D0
Always (Cond) (Note 2)
Write Conditions
Always (Note 2)
(Notes 1 3)
Stop Mode
Stop Mode
(Note 1)
Always
Always
Always
Always
N A
N A
Read
N A
Always
Always
Always
Always
Write
N A