dp83261 National Semiconductor Corporation, dp83261 Datasheet - Page 22

• Manufacturer Part Number: dp83261
• Description: Bmac Device Fddi Media Access Controller
• Manufacturer: National Semiconductor Corporation

5 0 Functional Description
by setting bit Function BCN to One Entry to the Claim State
can be forced by setting bit Function CLM to One
While in the Claim or Beacon state the Ring Engine will
transmit internally generated Claim or Beacon frames ex-
cept when an Immediate Claim or Beacon request is pres-
ent at the MA Request Interface signal RQCLM or
RQBCN is asserted and a frame is ready to be transmitted
At least one internally generated Claim or Beacon frame
must be transmitted before an Immediate Claim or Beacon
request is serviced It is possible for the internally generated
frame to return before the end of the requested frame has
been transmitted To allow time for the requested frame(s)
to be transmitted before leaving the Claim or Beacon state
bit ITR (for Claim) or bit IRR (for Beacon) of the Option
Register should be set to One
While an Immediate request is being serviced (from any
state) if bit IRPT of the Option Register is set to One (Inhibit
Repeat option) all received frames (except Lower Claim
and My Beacon frames) are ignored and the Immediate
request continues Lower Claim and My Beacon frames
can also be ignored by setting bit IRR of the Option Regis-
ter
5 10 FULL DUPLEX OPERATION
The BMAC device supports full duplex operation by
1 Suspending the Token Management and Token Recov-
2 Inhibiting the repetition of all PDUs (set Option IRPT)
3 Using the Immediate Service Class
Frames of any size may be transmitted or received subject
to the minimum length specified in Section 5 4
5 11 PARITY PROCESSING
The BMAC device contains five data interfaces as shown in
Table 5-6
Through Parity is supported on the internal data paths be-
tween any Request interface and any Indicate interface
Odd Parity is provided every clock on all data outputs and is
checked every clock on all data inputs Parity errors are not
propagated through the BMAC device (from the MAC Re-
quest and PHY Indication interface to the PHY Request in-
terface or from the PHY Indication interface to the MAC
Indication interface) Parity errors are isolated and resolved
ery protocols (set Option IRR)
MAC Request Interface
MAC Indication Interface
PHY Request Interface
PHY Indication Interface
Control Interface
Interface
(Continued)
TABLE 5-6 BMAC Device Parity
MRD(7 0)
PRD(7 0)
CBD(7 0)
PID(7 0)
MID(7 0)
Parity
PRC
PIC
On
22
When parity is not used on an Interface the parity provided
by the BMAC device for its outputs may be ignored For the
BMAC device’s inputs the result of the parity check is used
only if parity on that Interface is enabled
Interface parity is enabled by setting the appropriate bit in
the Mode register Mode CBP for Control Bus Parity Mo-
de PIP for PHY Indication parity and Mode MRP for MAC
Request Parity A Master Reset (Function MARST) disables
parity on all interfaces
On the PHY Request interface parity is generated for inter-
nally sourced fields (such as the SA or FCS on frames when
not using SA or FCS transparency and internally generated
Beacon Claim and Void frames) In REV 1 of the BMAC
device MRP is passed transparently to PRP for externally
sourced fields independent of the value of the Mode MRP
In all later revisions correct Odd parity is always generated
for PRP This allows through parity support at the PHY inter-
face even if parity is not used at the MAC interface This is
very desirable since every byte of data that traverses the
ring travels across the PHY Interface which is actually part
of the ring
Through parity is not supported in the Control Interface Reg-
isters and the Parameter RAM Parity is generated and
stripped at the Control Interface
Handling Parity Errors
Parity errors are reported in the Exception Status Register
when parity on that interface is enabled
A parity error at the PHY interface (when Mode PIP is set) is
treated as a code violation and ESR PPE is set If the parity
error occurs in the middle of a PDU (token or frame) recep-
tion the PDU is stripped a Format Error is signaled
(FOERROR) and the Lost Count is incremented
A parity error at the MAC Interface (when Mode MRP is set)
during a frame transmission from the MAC interface (while
TXACK is asserted) causes the frame transmission to be
aborted When a frame is aborted a Void frame is transmit-
ted to reset every station’s TVX timer A parity error (when
enabled) causes ESR MPE to be set
A parity error at the Control Interface (when Mode CBP is
set) will cancel the current write access ESR CPE is set to
indicate that a parity error occurred and ESR CCE is set to
indicate that the write was not performed
Parity
MRP
PRP
CBP
MIP
PIP
Direction
I O
O
O
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