lan9311 Standard Microsystems Corp., lan9311 Datasheet - Page 255
lan9311
Manufacturer Part Number
lan9311
Description
Lan9311/lan9311i Two Port 10/100 Managed Ethernet Switch With 16-bit Non-pci Cpu Interface
Manufacturer
Standard Microsystems Corp.
Datasheet
1.LAN9311.pdf
(460 pages)
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface
Datasheet
SMSC LAN9311/LAN9311i
14.2.8.6
31:16
BITS
15
14
13
12
10
11
9
8
RESERVED
(See
Next Page
This bit indicates the emulated link partner PHY next page capability and is
always 0.
0: Link partner PHY does not advertise next page capability
1: Link partner PHY advertises next page capability
Acknowledge
This bit indicates whether the link code word has been received from the
partner and is always 1.
0: Link code word not yet received from partner
1: Link code word received from partner
Remote Fault
Since there is no physical link partner, this bit is not used and is always
returned as 0.
RESERVED
Asymmetric Pause
This bit indicates the emulated link partner PHY asymmetric pause
capability.
0: No Asymmetric PAUSE toward link partner
1: Asymmetric PAUSE toward link partner
Pause
This bit indicates the emulated link partner PHY symmetric pause capability.
0: No Symmetric PAUSE toward link partner
1: Symmetric PAUSE toward link partner
100BASE-T4
This bit indicates the emulated link partner PHY 100BASE-T4 capability.
This bit is always 0.
0: 100BASE-T4 ability not supported
1: 100BASE-T4 ability supported
100BASE-X Full Duplex
This bit indicates the emulated link partner PHY 100BASE-X full duplex
capability.
0: 100BASE-X full duplex ability not supported
1: 100BASE-X full duplex ability supported
Virtual PHY Auto-Negotiation Link Partner Base Page Ability Register (VPHY_AN_LP_BASE_ABILITY)
This read-only register contains the advertised ability of the link partner’s PHY and is used in the Auto-
Negotiation process with the Virtual PHY. Because the Virtual PHY does not physically connect to an
actual link partner, the values in this register are emulated as described below.
Note
14.33)
Offset:
Index (decimal):
1D4h
5
DESCRIPTION
DATASHEET
255
Size:
32 bits
TYPE
RO
RO
RO
RO
RO
RO
RO
RO
RO
Revision 1.2 (04-08-08)
Note 14.34
Note 14.34
Note 14.34
Note 14.35
Note 14.35
Note 14.34
Note 14.36
DEFAULT
0b
1b
0b
0b
-
-
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