lan9311 Standard Microsystems Corp., lan9311 Datasheet - Page 397

• Manufacturer Part Number: lan9311
• Description: Lan9311/lan9311i Two Port 10/100 Managed Ethernet Switch With 16-bit Non-pci Cpu Interface
• Manufacturer: Standard Microsystems Corp.

Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface
Datasheet
SMSC LAN9311/LAN9311i
14.5.3.26
BITS
31:8
6:5
4:0
7
RESERVED
Ingress Rate RnW
These bits specify a read(1) or write(0) command.
Type
These bits select between the ingress rate metering/color table registers as
follows:
00 = RESERVED
01 = Committed Information Rate Registers
10 = Committed Burst Register
11 = Excess Burst Register
CIR Address
These bits select one of the 24 Committed Information Rate registers.
When Rate Mode is set to Source Port & Priority in the
Ingress Rate Configuration Register
set of 8 registers (CIR addresses 0-7) are for to Port 0, the second set of 8
registers (CIR addresses 8-15) are for Port 1, and the third set of registers
(CIR addresses 16-23) are for Port 2. Priority 0 is the lower register of each
set (e.g. 0, 8, and 16).
When Rate Mode is set to Source Port Only, the first register (CIR address
0) is for Port 0, the second register (CIR address 1) is for Port 1, and the
third register (CIR address 2) is for Port 2.
When Rate Mode is set to Priority Only, the first register (CIR address 0) is
for priority 0, the second register (CIR address 1) is for priority 1, and so
forth up to priority 23.
Note:
Switch Engine Ingress Rate Command Register (SWE_INGRSS_RATE_CMD)
This register is used to indirectly read and write the ingress rate metering/color table registers. A write
to this address performs the specified access.
For a read access, the Operation Pending bit in the
Register (SWE_INGRSS_RATE_CMD_STS)
Engine Ingress Rate Read Data Register (SWE_INGRSS_RATE_RD_DATA)
F o r a w r i t e a c c e s s , t h e
(SWE_INGRSS_RATE_WR_DATA)
Engine Ingress Rate Command Status Register (SWE_INGRSS_RATE_CMD_STS)
command is finished.
For details on 16-bit wide Ingress Rate Table registers indirectly accessible by this register, see
Section 14.5.3.26.1
Values outside of the valid range may cause unexpected results.
Register #:
below.
184Bh
DESCRIPTION
(SWE_INGRSS_RATE_CFG), the first
DATASHEET
S w i t c h E n g i n e I n g r e s s R a t e W r i t e D a t a R e g i s t e r
should be written first. The Operation Pending bit in the
397
(uses CIS Address field)
indicates when the command is finished. The
Size:
Switch Engine
Switch Engine Ingress Rate Command Status
32 bits
TYPE
can then be read.
R/W
R/W
R/W
RO
Revision 1.2 (04-08-08)
indicates when the
DEFAULT
00b
0b
0h
-
Switch
Switch