lan9311 Standard Microsystems Corp., lan9311 Datasheet - Page 454

• Manufacturer Part Number: lan9311
• Description: Lan9311/lan9311i Two Port 10/100 Managed Ethernet Switch With 16-bit Non-pci Cpu Interface
• Manufacturer: Standard Microsystems Corp.

Revision 1.2 (04-08-08)
15.5.9
SYMBOL
t
cycle
t
t
t
t
t
t
asu
dsu
csh
csl
ah
dh
A[2:1], END_SEL
TX Data FIFO Direct PIO Write Cycle Timing
Please refer to
description of this mode.
FIFO_SEL
Note: A TX Data FIFO direct PIO write cycle begins when both nCS and nWR are asserted. The
nCS, nWR
Write Cycle Time
nCS, nWER Assertion Time
nCS, nWR De-assertion Time
Address, FIFO_SEL Setup to nCS, nWR Assertion
Address, FIFO_SEL Hold Time
Data Setup to nCS, nWR De-assertion
Data Hold Time
D[15:0]
cycle ends when either or both nCS and nWR are de-asserted. They may be asserted and de-
asserted in any order.
Table 15.13 TX Data FIFO Direct PIO Write Cycle Timing Values
Figure 15.9 TX Data FIFO Direct PIO Write Cycle Timing
Section 8.5.9, "TX Data FIFO Direct PIO Writes," on page 112
DESCRIPTION
t
asu
DATASHEET
454
Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface
t
csl
t
t
cycle
dsu
MIN
45
32
13
0
0
7
0
t
dh
t
ah
TYP
t
csh
SMSC LAN9311/LAN9311i
MAX
for a functional
Datasheet
UNITS
nS
nS
nS
nS
nS
nS
nS