lan9311 Standard Microsystems Corp., lan9311 Datasheet - Page 318

• Manufacturer Part Number: lan9311
• Description: Lan9311/lan9311i Two Port 10/100 Managed Ethernet Switch With 16-bit Non-pci Cpu Interface
• Manufacturer: Standard Microsystems Corp.

Revision 1.2 (04-08-08)
1882h-1BFFh
REGISTER #
185Bh-187Fh
1853h-1854h
184Ch
184Dh
1C00h
1C01h
1C02h
184Ah
184Bh
184Eh
184Fh
185Ah
1849h
1850h
1851h
1852h
1855h
1856h
1857h
1858h
1859h
1880h
1881h
Table 14.12 Indirectly Accessible Switch Control and Status Registers (continued)
SWE_INGRESS_RATE_CMD
SWE_INGRESS_RATE_CFG
SWE_INGRESS_RATE_CMD_STS
SWE_INGRESS_RATE_WR_DATA
SWE_INGRESS_REGEN_TBL_MII
SWE_INGRESS_RATE_RD_DATA
SWE_FILTERED_CNT_MII
SWE_ADMT_N_MEMBER
SWE_INGRESS_REGEN_TBL_1
SWE_INGRESS_REGEN_TBL_2
SWE_LRN_DISCRD_CNT_MII
SWE_FILTERED_CNT_1
SWE_FILTERED_CNT_2
SWE_LRN_DISCRD_CNT_1
SWE_LRN_DISCRD_CNT_2
BM_FC_PAUSE_LVL
BM_DROP_LVL
RESERVED
RESERVED
RESERVED
RESERVED
SWE_IMR
SWE_IPR
SYMBOL
BM_CFG
Buffer Manager (BM) CSRs
DATASHEET
Switch Engine Admit Non Member Register,
Switch Engine Ingress Rate Configuration Register,
Section 14.5.3.25
Switch Engine Ingress Rate Command Register,
Section 14.5.3.26
Switch Engine Ingress Rate Command Status Register,
Section 14.5.3.27
Switch Engine Ingress Rate Write Data Register,
Section 14.5.3.28
Switch Engine Ingress Rate Read Data Register,
Section 14.5.3.29
Switch Engine Port 0 Ingress Filtered Count Register,
Section 14.5.3.30
Switch Engine Port 1 Ingress Filtered Count Register,
Section 14.5.3.31
Switch Engine Port 2 Ingress Filtered Count Register,
Section 14.5.3.32
Switch Engine Port 0 Ingress VLAN Priority Regeneration
Register,
Switch Engine Port 1 Ingress VLAN Priority Regeneration
Register,
Switch Engine Port 2 Ingress VLAN Priority Regeneration
Register,
Switch Engine Port 0 Learn Discard Count Register,
Section 14.5.3.36
Switch Engine Port 1 Learn Discard Count Register,
Section 14.5.3.37
Switch Engine Port 2 Learn Discard Count Register,
Section 14.5.3.38
Reserved for Future Use
Switch Engine Interrupt Mask Register,
Switch Engine Interrupt Pending Register,
Reserved for Future Use
Buffer Manager Configuration Register,
Buffer Manager Drop Level Register,
Section 14.5.4.3
Reserved for Future Use
Reserved for Future Use
Buffer Manager Flow Control Pause Level Register,
318
Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface
Section 14.5.3.33
Section 14.5.3.34
Section 14.5.3.35
REGISTER NAME
Section 14.5.4.2
Section 14.5.3.39
Section 14.5.4.1
SMSC LAN9311/LAN9311i
Section 14.5.3.40
Section 14.5.3.24
Datasheet