peb20532 Infineon Technologies Corporation, peb20532 Datasheet - Page 121

• Manufacturer Part Number: peb20532
• Description: 2 Channel Serial Optimized Communication Controller
• Manufacturer: Infineon Technologies Corporation

5.2
5.2.1
Each register description is organized in three parts:
• a head with general information about reset value, access type (read/write), offset
• a table containing the bit information (name of bit positions);
• a section containing the detailed description of each bit.
Register 1
CPU Accessibility:
Reset Value:
Offset Address:
typical usage:
Data Sheet
SWR
Bit
address and usual handling;
7
0
Detailed Register Description
Global Registers
Software Reset Command
Self clearing command bit:
bit=’0’
bit=’1’
GCMDR
Global Command Register
6
0
read/write
00
00
written by CPU,
evaluated by SEROCCO-M
H
H
No software reset command is issued.
Causes SEROCCO-M to perform a complete reset
identical to hardware reset.
5
0
Global Command Bits
4
0
121
3
0
2
0
Register Description
1
0
PEB 20532
PEF 20532
2000-09-14
SWR
0