peb20532 Infineon Technologies Corporation, peb20532 Datasheet - Page 144

• Manufacturer Part Number: peb20532
• Description: 2 Channel Serial Optimized Communication Controller
• Manufacturer: Infineon Technologies Corporation

Data Sheet
SYNC
RLI
DPLA
Synchronization Status
This bit indicates whether the receiver is in synchronized state. After a
’HUNT’ command ’SYNC’ bit is cleared and the receiver starts searching
for a SYNC character. When found the ’SYNC’ status bit is set
immediately, an SCD-interrupt is generated (if enabled) and receive data
is forwarded to the receiver FIFO.
SYNC=’0’
SYNC=’1’
Receive Line Inactive
This bit indicates that neither flags as interframe time fill nor data are
being received via the receive line.
RLI=’0’
RLI=’1’
Note: A receive clock must be provided in order to detect the receive line
DPLL Asynchronous
This bit is only valid if the receive clock is recovered by the DPLL and
FM0, FM1 or Manchester data encoding is selected. It is set when the
DPLL has lost synchronization. In this case reception is disabled
(receive abort condition) until synchronization has been regained. In
addition transmission is interrupted in all cases where transmit clock is
derived from the DPLL (clock mode 3a, 7a). Interruption of transmission
is performed the same way as on deactivation of the CTS signal.
DPLA=’0’
DPLA=’1’
state.
Synchronization is lost or not yet achieved.
(after reset or after new ’HUNT’ command has been
issued and before SYNC character is found)
The receiver is in synchronized state.
Receive line is active, no constant high level is detected.
Receive line is inactive, i.e. more than 7 consecutive ’1’
are detected on the line.
DPLL is synchronized.
DPLL is asynchronous (re-synchronization process is
started automatically).
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Register Description (STARH)
(bisync mode)
PEB 20532
PEF 20532
(hdlc mode)
(all modes)
2000-09-14