peb20532 Infineon Technologies Corporation, peb20532 Datasheet - Page 170

• Manufacturer Part Number: peb20532
• Description: 2 Channel Serial Optimized Communication Controller
• Manufacturer: Infineon Technologies Corporation

Data Sheet
DXS
XBRK
ESS7
STOP
Disable Storage of XON/XOFF Characters
In ASYNC mode, XON/XOFF characters might be filtered out or stored
to the SCC receive FIFO:
DXS=’0’
DXS=’1’
Transmit Break
XBRK=’0’
XBRK=’1’
Enable SS7 Mode
This bit is only valid in HDLC mode only.
ESS7=’0’
ESS7=’1’
Note: If SS7 mode is enabled, ’Address Mode 0’ must be selected by
Stop Bit number
This bit selects the number of stop bits per ASYNC character:
STOP=’0’
STOP=’1’
setting bit field CCR2L:MDS(1:0) to ’10’ and bit CCR2L:ADM to ’0’.
All received characters including XON/XOFF characters
are stored in the receive FIFO.
XON/XOFF characters are filtered out and not stored in
the receive FIFO.
Normal transmit operation.
Forces the TxD pin to ’low’ level immediately (break
condition), regardless of any character being currently
transmitted. This command is executed immediately with
the next rising edge of the transmit clock and further
transmission is disabled. The currently sent character is
lost.
Data stored in the SCC transmit FIFO will be sent as soon
as the break condition is cleared (XBRK=’0’). A transmit
reset command (bit ’XRES’ in register CMDRL) does NOT
clear the break condition automatically.
Disable signaling system #7 (SS7) support.
Enable signaling system #7 (SS7) support.
1 stop bit per character.
2 stop bits per character.
5-170
Register Description (CCR3H)
(async mode)
(async mode)
(async mode)
PEB 20532
PEF 20532
(hdlc mode)
2000-09-14