peb20532 Infineon Technologies Corporation, peb20532 Datasheet - Page 150

• Manufacturer Part Number: peb20532
• Description: 2 Channel Serial Optimized Communication Controller
• Manufacturer: Infineon Technologies Corporation

Data Sheet
HUNT
RFRD
RRES
Enter Hunt State Command
Self-clearing command bit:
HUNT=’1’
Receive FIFO Read Enable Command
Self-clearing command bit:
RFRD=’1’
Receiver Reset Command
Self-clearing command bit:
RRES=’1’
This command forces the receiver to enter its ’HUNT’
state immediately. Thus synchronization is ’lost’ and the
receiver starts searching for new SYNC characters.
This command forces insertion of a ’block end’ condition
into the RFIFO before the receive FIFO threshold is
exceeded or a block end condition (termination character
detected or time-out) is fulfilled. The execution of this
command is reported with a TCD interrupt.
The SCC receive FIFO is cleared and the receiver
protocol engines are reset to their initial state.
The SCC receive FIFO accepts new receive data from the
protocol engine immediately after receiver reset
procedure.
It is recommended to disable data reception before
issuing a receiver reset command by setting bit
CCR3L.RAC = ’0’ and enabling data reception afterwards.
A ’receiver reset’ command is recommended after all
changes in protocol mode configurations (switching
between the protocol engines HDLC/ASYNC/BISYNC or
sub-modes of HDLC).
5-150
Register Description (CMDRH)
(async/bisync modes)
(bisync mode)
PEB 20532
PEF 20532
(all modes)
2000-09-14