peb20532 Infineon Technologies Corporation, peb20532 Datasheet - Page 146

• Manufacturer Part Number: peb20532
• Description: 2 Channel Serial Optimized Communication Controller
• Manufacturer: Infineon Technologies Corporation

Data Sheet
Register 19
CPU Accessibility:
Reset Value:
Offset Address:
typical usage:
Register 20
CPU Accessibility:
Reset Value:
Offset Address:
typical usage:
The command register contains self-clearing command bits. The command bits read a
’1’ until the corresponding command is executed completely.
Bit
Bit
H
A
B
H
A
B
RMC
RMC
RMC
STI
STI
STI
7
7
Timer
CMDRL
Command Register (Low Byte)
CMDRH
Command Register (High Byte)
TRES
TRES
TRES
RNR
6
6
0
0
read/write
00
Channel A
14
written by CPU, evaluated by SEROCCO-M
read/write
00
Channel A
15
written by CPU, evaluated by SEROCCO-M
H
H
H
H
TXON
XIF
5
0
5
0
0
0
Channel B
64
Channel B
65
Receiver Commands
H
H
XRES
XRES
XRES
5-146
4
4
0
0
0
Transmitter Commands
RSUC
HUNT
XF
XF
XF
3
3
0
Register Description (CMDRL)
XME
XME
XME
2
2
0
0
0
RFRD
RFRD
XREP
XREP
XREP
1
1
0
PEB 20532
PEF 20532
2000-09-14
TXOFF
RRES
RRES
RRES
0
0
0
0