peb20532 Infineon Technologies Corporation, peb20532 Datasheet - Page 198

• Manufacturer Part Number: peb20532
• Description: 2 Channel Serial Optimized Communication Controller
• Manufacturer: Infineon Technologies Corporation

Data Sheet
Register 59
CPU Accessibility:
Reset Value:
Offset Address:
typical usage:
Register 60
CPU Accessibility:
Reset Value:
Offset Address:
typical usage:
Bit
Bit
H
A
B
H
A
B
SRC
SRC
SRC
7
7
TIMR2
Timer Register 2
TIMR3
Timer Register 3
6
6
0
0
0
read/write
00
Channel A
3C
written by CPU;
read and evaluated by SEROCCO-M
read/write
00
Channel A
3D
written by CPU;
read and evaluated by SEROCCO-M
H
H
H
H
5
5
0
0
0
Channel B
8C
Channel B
8D
Timer Configuration
H
H
TMD
TVALUE(23:16)
TVALUE(23:16)
TVALUE(23:16)
5-198
4
4
0
0
Timer Value
3
3
0
0
0
Register Description (TIMR2)
2
2
CNT(2:0)
CNT(2:0)
CNT(2:0)
1
1
PEB 20532
PEF 20532
2000-09-14
0
0