w83l950d Winbond Electronics Corp America, w83l950d Datasheet - Page 68

• Manufacturer Part Number: w83l950d
• Description: Peripheral Personal Computer Keyboard Controller
• Manufacturer: Winbond Electronics Corp America

14. PWM
There are four PWM output in the Winbond Keyboard controller. The PWM0 and 1 are compatible with
the 3886 group of the MITSUBISHI and is 14-bit controller. The PWM2 and 3 is new feature of the
Winbond keyboard controller. The relative register of PWM2 and 3 is defined on Advance Register
region. And is described in the later chapter.
Note:
The PWM 0,1 enable bit are located in Port Control Register 1(PCTRL1).
The PWM 0,1 output pin selection is located in AD control register (ADCON).
14.1 PWM 0 and 1 Operation
The 14-bit PWM data is divided into the low-order six bits and the high-order eight bits in the PWM latch
and are fixed frequency at 15.6KHz. The high-order eight bits PWMH determines how long an
"H"-Level signal is output during each period. Each period is divided into 256 grades but 255, hence to
set PWMH to maximum 255 may NOT result in Always High output on PWM signal, there is a bit pulse
low occurred. The low-order six bits PWML is used to adjust the PWM sub-period, however this
sub-period adjustment is no much useful in most application.
For example:
14.2 Transfer From Register to Latch
Data written to the PWML register is transferred to the PWM latch at each PWM period (every 4096 us),
and data written to the PWMH register is transferred to the PWM latch at each sub-period (every 64 us).
The signal is output to the PWM output pin is corresponding to the contents of this latch. When the
PWML register is read, the latch contents are read. However, bit 7 of the PWML register indicates
whether the transfer to the PWM latch is completed; the transfer is completed when bit 7 is '0" and it is
not done when bit 7 is '1".
14.3 PWM0H register (PWM0H)
14.4 PWM0L register (PWM0L)
14.5 PWM1H register (PWM1H)
SFR address
Default value
SFR address
Default value
SFR address
Default value
Set PWMH to 192, PWML to 0, may result in a 75% duty cycle.
Set PWMH to 127, PWML to 0, may result in a 50% duty cycle.
and so on.
0xD4
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0xD5
x0xxxxxxb
0xD6
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Publication Release Date: June 23, 2003
W83L950D
Revision 1.0