w83l950d Winbond Electronics Corp America, w83l950d Datasheet - Page 91
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w83l950d
Manufacturer Part Number
w83l950d
Description
Peripheral Personal Computer Keyboard Controller
Manufacturer
Winbond Electronics Corp America
Datasheet
1.W83L950D.pdf
(105 pages)
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22. AUXILIARY SMBUS ADDRESS AND REGISTERS
22.1 Auxiliary SMBus Host Status Register (AHSR)
Advanced SFR Address
Default Value
Attribute:
Bit
7
6
5
4
3
2
1
0
NOT ACK Command Received (NOT_ACK).
1= SMBus controller cannot receive the acknowledge command from the host writing
Receive FIFO Full (RX_FULL).
1= The receive data FIFO has filled 16-bytes data from the SMBus receiver. Write 1 to clear
Receiver FIFO Time-out (RXTIMEOUT).
1 = If the received data in the FIFO does not over the FIFO threshold level and the time is
SMBus FAILED (FAIL).
1 = The source of the interrupt was a failed bus transaction. This bit is set in response to the
SMBus Collision (BUS_COL).
1 = The source of the interrupt was a transaction collision or arbitration fail. Write 1 clear this
bit.
Device Error (DEV_ERR).
1 = Host Device Time-out Error.
Writing 1 to this bit. The micro-controller will then de-assert the interrupt.
REMOTE TX_TIMEOUT (RE_TXTIMEOUT)
1 = When local device is in receiver mode, set this bit to indicate remote device transmission
timeout.
HOST_BUSY (H_BUSY)- Read Only.
1 = SMBus Controller is processing a command from the host interface or receiving SMBus
data.
0 = SMBus controller host interface is not processing a command.
address or data. Write 1 to clear this bit.
this bit
over 1 ms, the interrupt also be generated to inform the micro-controller. Perhaps this bit is
always inactive in the polling mode or using package-end status in the interrupt mode. Write
1 clear this bit. This bit is a source of interrupt.
KILL bit being set to terminate the host transaction. Write 1 clear this bit.
0x28
0x00
Read/Write Clear
- 82 -
Description
W83L950D
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