w83l950d Winbond Electronics Corp America, w83l950d Datasheet - Page 82

• Manufacturer Part Number: w83l950d
• Description: Peripheral Personal Computer Keyboard Controller
• Manufacturer: Winbond Electronics Corp America

20.4 PS/2 Status_2 Registers (PS2STS_2)
When operating in PS2 receiving mode, PS2_T/R is 0, this bit is set on either of 4 conditions
asserted. And PS2 control logic will generate a 300us LOW pulse on CLK line following the bit set.
An Interrupt is generated on the low to high transition of the REC_TIMEOUT bit. The
REC_TIMEOUT bit is cleared when the Status Register is read.
When operating in PS2 receiving mode, after a data byte was received successfully, and no FE, PE
and REC_TIMEOUT, this bit is set until a read of Receive Register. An Interrupt is generated on the
low to high transition of the RDATA_RDY bit. Switching PS2_EN or PS2_T/R bits under certain
conditions will also clear or set this bit in exception.
1) When the receiver bit time (time between falling edges) exceeds 300us.
When a BUSY bit is set, the corresponding PS2 channel is busy in receiving data. Otherwise, the
channel is idle.
Bit 4: XMIT_IDLE - Transmitter Idle:
Bit3: FE - Framing Error
Bit2: PE Parity Error:
Bit 1: REC_TIMEOUT
2) If the time from the 1st (start) bit to the 10th (parity) bit exceeds 2ms.
3) On a receive parity error along with the parity error (PE) bit.
4) On a receive framing error due to an incorrect STOP bit along with the framing error (FE) bit.
Bit 0: RDATA_RDY Receive Data Ready:
Advance address
Bit 0: Port 1 PS2 busy
Bit 1: Reserved.
Bit 2: Port 2 PS2 busy
The XMIT_IDLE bit is a status bit indicating whether the PS2 channel is actively transmitting
data to the auxiliary device. After a success of writing to the Transmit Register the
XMIT_IDLE bit will be cleared to 0 until one of the following conditions occurred.
1) The falling edge of the 11th CLK; upon a Transmit Timeout condition (XMIT_TIMEOUT
2) Upon the PS2_T/R bit being written to 0.
3) Upon the PS2_EN bit being written to 0.
An interrupt is generated on the low to high transition of XMIT_IDLE.
If the received stop bit (11th bit) is different with the expected setting of PS2CON register,
the FE and REC_TIMEOUT are set and an interrupt also generated.
If the received parity bit (10th bit) is different with the expected setting of PS2CON register,
the PE and REC_TIMEOUT are set and an interrupt also generated.
= 0, IDLE
= 1, BUSY
goes high)
0x1B
- 73 -
Publication Release Date: June 23, 2003
W83L950D
Revision 1.0