w83l950d Winbond Electronics Corp America, w83l950d Datasheet - Page 74

• Manufacturer Part Number: w83l950d
• Description: Peripheral Personal Computer Keyboard Controller
• Manufacturer: Winbond Electronics Corp America

17.2 Comparator Data Register (CMPD)
18. WATCHDOG TIMER
The watchdog timer gives a mean of returning to the reset state when a program cannot run on a
normal loop (for example, because of a software run-away). The watchdog timer consists of an 8-bit
timer L and an 8-bit timer H.
17.1. Standard Operation of Watchdog Timer
17.2. Initial Value of Watchdog Timer
17.3. Watchdog Timer H Count Source Selection Bit Operation
selection bit (bit 7) of the serial 1/O2 control register (SIO2CON) (The internal fixed analog
volt- age becomes about 4 5 V at VCC - 50 V). When setting "0" to the comparator reference
input selection bit, the P00/P3REF pin be- comes the comparator reference power source input
pin and it is possible to input the comparator reference power source optionally from the
external.
The voltage comparison is immediately performed by the writing operation to the comparator
data register (CMPD). If the analog input voltage is greater than the internal reference voltage,
each bit of this register is '1 "; if it is less than the internal reference voltage, each bit of this
register is "0" .To perform another comparison, the voltage comparison must be performed
again by writing to the comparator data register (CMPD).
SFR address
Default value
When any data is not written into the watchdog timer control register (WDTCON) after
resetting, the watchdog timer is in the stop state. The watchdog timer starts to count down by
writing an optional value into the watchdog timer control register (WDTCON) and an internal
reset occurs at an underflow of the watchdog timer H. Accordingly, programming is usually
performed so that writing to the watchdog timer control register (WDTCON) should be started
before an underflow. When the watchdog timer control register (WDTCON) is read, the values
of the high-order 6 bits of the watchdog timer H, IDLE mode disable bit, and watchdog timer H
count source selection bit are read.
At reset or writing to the watchdog timer control register (WDTCON), each watchdog timer H
and L is set to 0FFh.
Bit 7 of the watchdog timer control register (WDTCON) permits selecting a watchdog timer H
count source. When this bit is set to '0", the count source becomes the underflow signal of
watchdog timer L. The detection time is set to f(XIN) = 131.072 ms at 8 MHz frequency and
f(XCIN) = 32.768 s at 32 KHz frequency. When this bit is set to '1", the count source becomes
the signal divided by 16 for f (XlN) or f (XCIN). The detection time in this case is set to
512 us at 8 MHz frequency and f(XClN) = 128 ms at 32 kHz frequency. This bit is cleared to '0"
after reset.
0xE7
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Publication Release Date: June 23, 2003
W83L950D
Revision 1.0
f
(XlN) =