w83l950d Winbond Electronics Corp America, w83l950d Datasheet - Page 79

• Manufacturer Part Number: w83l950d
• Description: Peripheral Personal Computer Keyboard Controller
• Manufacturer: Winbond Electronics Corp America

20. PS/2 DEVICE INTERFACE
The Winbond Keyboard controller has three hardware PS/2 channels. Each of them uses the
synchronous serial protocol to communicate with the auxiliary device. Each PS/2 channel has two
exclusive signal lines, Clock and Data, which are bi-directional and employed as open drain structure.
The relative register is defined on Advance register space .The PS2DATA, PS2CON and PS2STS is
defined individually for each PS/2 channel. PS2STS_2 is only one register for all PS/2 register to
indicate each PS2 channel’s busy state.
20.1 PS/2 Transmit and Receive DATA Registers (PS2DATA)
20.1.1 Transmit Register
20.1.2 Receive Register
Advance address 0x10, 0x14, 0x18
The PS2 control logic employs two internal registers, Transmit Register and Receive Register,
to serve the data transmission and reception. In order to these two registers shared the same
SFR address, accessing to either of them should obey the rule described below.
When PS2_T/R, PS2_EN, and XMIT_IDLE are set, and RDATA_RDY is cleared, a data
writing to this register invokes a transmission on PS2 channel. If any of three bits (PS2_T/R,
PS2_EN, and XMIT_IDLE) are not set, then writes to this register is ignored. Even If PS2_T/R,
PS2_EN, and XMIT_IDLE are all set but RDATA_RDY is set, a data writing to this register will
not kick off a transmission but stayed in Transmit Register until the RDATA_RDY is cleared (by
a read of Receive Register). A data where stored in Receive Register should be read before
next transmission.
After a success of transmission or upon a Transmit Time-out condition, the PS2_T/R bit is
automatically cleared and the XMIT_IDLE bit is automatically set. Before transfer data to an
auxiliary device, be sure the PS2_T/R bit is set to a ‘1’ is required. An interrupt is generated on
the low to high transition of XMIT_IDLE. All bits of this register are write-only.
When PS2_EN = 1 and PS2_T/R = 0, the PS2 Channel is set to automatically receive mode,
which both CLK and DATA signals are float to indicate the channel now is in “Auxiliary device
transmit permission mode” by pull-up them to 1.
After a success of reception, a data is placed in this register and the RDATA_RDY bit is set
and the CLK line is driven to LOW until a read of this register. Also the RDATA_RDY is cleared
after this read. This feature intends to provide a fluent reception flow control. Besides, there
are some of auxiliary device has a restriction of data package rate, the firmware should read
the data from this register as quickly as possible to maintain the best performance. All bits of
this register are read-only.
The Receive Register is initialized to 0FFh after a read or after a Timeout has occurred. An
interrupt is generated on the low to high transition of RDATA_RDY.
If a receive timeout (REC_TIMEOUT=1) or a transmit timeout (XMIT_TIMEOUT =1) occurred,
the PS2 control logic will drive CLK LOW for 300us to signal the auxiliary device there is an
error occurred. During this 300us CLK LOW period, writing to the Transmit Register is also
permitted. But a data transmission will be invoked when all condition asserted.
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W83L950D