saa6703ah NXP Semiconductors, saa6703ah Datasheet - Page 12

• Manufacturer Part Number: saa6703ah
• Description: Xga Analog Input Flat Panel Controller.
• Manufacturer: NXP Semiconductors

Philips Semiconductors
7
In this chapter detailed information for the general
configuration of the SAA6703AH is provided as well as
detailed background information belonging to certain
submodules of the device. Due to the high complexity of
the device functionality this section should be studied very
carefully.
7.1
7.1.1
The SAA6703AH operation is controlled by configuration
parameters, that can be multiple-bit words or consist of
only a single bit. The configuration parameters are
mapped to bits of the 8 bit I
that are accessible via the I
data such as measurement results or interrupt states is
mapped to readable I
The I
register can only be accessed if the particular page is
activated with the exception of global registers, so
non-global registers are addressed by the I
subaddress in combination with the matching active page,
but global registers are addressed by the subaddress
independently of the active page.
The global registers are mapped to I
F8H to FFH. The active page is defined by page_select at
subaddress FFH. In general, registers belonging to the
same functional unit are mapped onto the same page. The
I
Table 2 I
2004 Apr 01
2
C-bus register pages are shown in Table 2.
XGA analog input flat panel controller
PAGE
FUNCTIONAL DESCRIPTION
10
11
2
0
1
2
3
4
5
6
7
8
9
C-bus registers are organized in pages. Generally, a
Programming registers
C
2
ONFIGURATION PARAMETER MAPPING
C-bus register pages
control unit and clock generator
ADC control
mode detection
auto-adjustment
input interface and picture generator
colour processing
decoupling FIFO
scalers
OSD
OSD colour definition
gamma correction and dithering
TFT output interface
2
C-bus registers.
FUNCTIONAL UNIT
2
2
C-bus programming registers,
C-bus interface. Read-out
2
C-bus subaddresses
2
C-bus
12
7.1.2
The I
clock pin SCL and the serial data pin SDA.
7.1.2.1
The I
to 3.4 Mbits/s, given that a minimum system clock rate is
provided. The required system clock rate depends on the
target I
pin SCL, and the spike suppression mode selected by
iic_spike_mode in register IIC_MODE (03H at page 0) as
shown in Table 3. If iic_spike_mode is set to 2, a high
oversampling rate is used and the most effective spike
suppression is provided.
Table 3 I
7.1.2.2
The SAA6703AH only operates as a slave and the clock
pin SCL is exclusively input. Data is transmitted and
received at I/O pin SDA. The SDA is an open-drain stage
with an external pull-up resistor. When a logic 0 is applied,
the bus is pulled to LOW-level by the output buffer. When
a logic 1 is applied, the output buffer switches to 3-state
and the pull-up resistor pulls the bus up to HIGH-level.
Data transfers are initiated by an I
sending the start condition, which is a change from
HIGH-to-LOW level at SDA when SCL is at HIGH-level
(see Fig.3).
Data is transmitted byte wise. Data changes on SDA are
allowed only when SCL is at LOW-level and data is
sampled on the positive edge of SCL. The first transmitted
byte is the recipients I
transfer direction bit. All byte transfers are acknowledged
by the recipient by pulling SDA to LOW-level for the
following cycle.
iic_spike_
mode[1:0]
2
2
00
01
10
11
C-bus serial interface consists of two pins: the serial
C-bus interface supports transmission speeds of up
2
C-bus bit rate, which is the clock rate applied to
I
2
2
C-
Transmission bit rate
I
C-bus spike suppression modes
2
C-bus transmission timing
BUS INTERFACE
>6
bit rate
>6
bit rate
>16
bit rate
not used
SYSTEM
CLOCK
I
I
2
2
I
C-bus
C-bus
2
2
C-bus
C-bus device address and the data
2-out-of-2 filter
2-out-of-3 majority filter
4-out-of-4 filter
2
C-bus master device by
SAA6703AH
DESCRIPTION
Product specification