saa6703ah NXP Semiconductors, saa6703ah Datasheet - Page 39

• Manufacturer Part Number: saa6703ah
• Description: Xga Analog Input Flat Panel Controller.
• Manufacturer: NXP Semiconductors

Philips Semiconductors
7.4.2
The clock signals of auto-adjustment, downscaler,
upscaler and OSD module are powered-down
automatically during inactivity if programming bits
aaclk_auto, dscclk_auto, uscclk_auto and osdclk_auto
respectively in register CD_CLK_AUTO (11H) are set to
logic 1. Otherwise the clock signals are switched on and
off according to the state of bits aaclk_on, dscclk_on,
uscclk_on and osdclk_on respectively in register
CD_CLK_EN (10H).
The general configuration and the OSD configuration clock
signal are also powered-down during inactivity unless
forced active, when cfgclk_on or osd_cfgclk_on
respectively (CD_CLK_EN, 10H) is set to logic 1.
When automatic activation is selected, each clock signal is
active during either power-on or the programmable reset
of the specific domain and whenever the concerned
module is activated.
7.4.3
The SAA6703AH contains two PLLs:
The PLL programming registers are mapped to register
page 0.
2004 Apr 01
handbook, full pagewidth
Line-locked PLL generating the sample clock from the
hsync signal (see Fig.6)
PLL running on the system clock generating the panel
clock (see Fig.7).
XGA analog input flat panel controller
C
PLL
LOCK ACTIVATION CONTROL
PROGRAMMING
HS_PLL
VS_PLL
line_vs_pol
FREQUENCY
DETECTOR
PHASE
AND
line_hs_pol
Fig.6 Line PLL block diagram.
50 to 320 MHz
OSCILLATOR
line_pll_en
line_pll_n_div [ 11:0 ]
39
n-DIVIDER
The PLLs are activated by pll_en and line_pll_en and the
back-end clock PLL pre-divider by pll_pre_div_en at
register CD_PLL_CTRL (20H).
Bits line_pll_vs_pol and line_pll_hs_pol define the polarity
of the vertical and horizontal sync inputs. Each bit has to
be set to logic 1 in case of positive (active HIGH) polarity
of the corresponding sync signal; otherwise to logic 0.
The outputs for the pre-divider, n-divider and m-divider
ratios are set accordingly to bits pll_pre_div, pll_m_div,
pll_n_div, line_pll_m_div and line_pll_n_div at registers
CD_PLL_P_HI to CD_LPLL_LO (21H to 26H).
The pll_n_div is a programmable divider between
100 to 4096. The relation between hsync and pll_clk is:
pll_clk = pll_n_div
should be selected at minimum two times pll_clk.
The pll_m_div is a programmable divider between ‘00’ = 1,
‘01’ = 2, ‘10’ = 2, ‘11’ = 4 and limits the current controlled
oscillator tuning range.
The line PLL clock is finally phase shifted as defined in
steps of 11.25 degrees by line_pll_phase at register
CD_LPLL_PHA (27H).
For the auto-adjustment phase distortion measurement
register CD_LPLL_PD contains an alternative phase value
pd_pll_phase for the line PLL. Parameter phase_auto
enables switching between both phase values controlled
by the auto-adjustment if set to logic 1, or manual selection
by phase_select.
line_pll_m_div [ 1:0 ]
m-DIVIDER
hsync. The frequency of the oscillator
MHC215
2
line PLL
clock
SAA6703AH
Product specification