saa6703ah NXP Semiconductors, saa6703ah Datasheet - Page 37

• Manufacturer Part Number: saa6703ah
• Description: Xga Analog Input Flat Panel Controller.
• Manufacturer: NXP Semiconductors

Philips Semiconductors
7.2
The readable parameter device_id contains the IC version
code. The current version returns the code 131CH.
7.3
The external Power-on reset is active LOW and applied to
pin RST.
Front-end, back-end and the output interface can be
switched into the reset state individually by the I
programming using reset_fclk, reset_bclk and reset_oif at
register GC_RESET (FCH). Each domain reset is active if
the corresponding programming bit is set to logic 1.
2004 Apr 01
handbook, full pagewidth
XGA analog input flat panel controller
Device ID
Initialization
HS_PLL
VS_PLL
CLK
PANEL CLOCK
LINE-LOCKED
configuration
configuration
signals
signals
PLL
PLL
Fig.5 Clock distribution.
2
C-bus
vclk_in_en
bclk_in_en
0
1
0
1
37
line_pll_phase [ 4:0 ]
7.4
All clock management configuration registers are mapped
to register page 0.
A block diagram of the clock distribution is given in Fig.5.
The clock source for the decoupling FIFO is selected by
fifo_fclk. If fifo_fclk is set to logic 1, the front-end clock is
applied to the decoupling FIFO; otherwise the back-end
clock is used.
The decoupling FIFO always has to be supplied with the
clock signal of the higher clock rate.
PHASE
SHIFT
Clock management
4
2
frontend_bclk
cfgclk_select
clk_div4
vclk_in_en
0
1
0
1
0
1
VCLK (I/O)
front-end
ADC sample
back-end
system
configuration
clock
clock
clock
MHC279
clock
clock
SAA6703AH
Product specification