hyb18t512160afl-3.7 Infineon Technologies Corporation, hyb18t512160afl-3.7 Datasheet - Page 102

• Manufacturer Part Number: hyb18t512160afl-3.7
• Description: 512-mbit Ddr2 Sdram
• Manufacturer: Infineon Technologies Corporation

Table 54
Parameter
Address and control input pulse width
(each input)
Address and control input setup time
DQ low-impedance time from CK / CK
DQS low-impedance from CK / CK
Mode register set command cycle time
OCD drive mode output delay
Data output hold time from DQS
Data hold skew factor
Average periodic refresh Interval
Auto-Refresh to Active/Auto-Refresh command period
Read preamble
Read postamble
Active bank A to Active bank B command period
Internal Read to Precharge command delay
Write preamble
Write postamble
Write recovery time for write without Auto-Precharge
Write recovery time for write with Auto-Precharge
Internal Write to Read command delay
Exit power down to any valid command
(other than NOP or Deselect)
Exit active power-down mode to Read command (slow
exit, lower power)
Exit precharge power-down to any valid command
(other than NOP or Deselect)
Exit Self-Refresh to non-Read command
Exit Self-Refresh to Read command
1)
2) Timing that is not specified is illegal and after such an event, in order to guarantee proper operation, the DRAM must be
3) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a
4) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross.
5) Inputs are not recognized as valid until
6) The output timing reference voltage level is
Data Sheet
V
powered down and then restarted through the specified initialization sequence before normal operation can continue.
differential Slew Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode. For other
Slew Rates see Chapter 8 of this data sheet. Timings are further guaranteed for normal OCD drive strength (EMRS(1) A1
= 0) under the Reference Load for Timing Measurements according to Chapter 8.1 only.
The DQS/DQS, RDQS/RDQS, input reference level is the crosspoint when in differential strobe mode;
The input reference level for signals other than CK/CK, DQS/DQS, RDQS/RDQS is defined in Chapter 8.3 of this data
sheet.
recognized as low.
DDQ
= 1.8 V ± 0.1 V;
Timing Parameter by Speed Grade - DDR2-400
V
DD
= 1.8 V ± 0.1 V. See notes
V
REF
V
stabilizes. During the period before
TT
. See Chapter 8 for the reference load for timing measurements.
3)4)5)6)
103
Symbol
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
WR
t
t
t
t
t
t
IPW
IS
LZ(DQ)
LZ(DQS)
MRD
OIT
QH
QHS
REFI
RFC
RPRE
RPST
RRD
RTP
WPRE
WPST
WR
WTR
XARD
XARDS
XP
XSNR
XSRD
(base)
HYB18T512[40/80/16]0AF(L)–[3/3S/3.7/5]
DDR2-400
Min.
0.6
350
2
t
2
0
t
—
—
—
105
0.9
0.40
7.5
10
7.5
0.35
0.40
15
t
7.5
2
6 – AL
2
t
200
AC.MIN
HP
WR
RFC
x
–
/
t
t
AC.MIN
CK
+10
t
QHS
V
REF
stabilizes, CKE = 0.2 x
512-Mbit DDR2 SDRAM
Max.
—
—
t
t
—
12
—
450
7.8
3.9
—
1.1
0.60
—
—
—
—
0.60
—
—
—
—
—
—
—
AC.MAX
AC.MAX
Electrical Characteristics
09112003-SDM9-IQ3P
Unit
t
ps
ps
ps
t
ns
ps
µs
µs
ns
t
t
ns
ns
ns
t
t
ns
t
ns
t
t
t
ns
t
Rev. 1.6, 2005-08
CK
CK
CK
CK
CK
CK
CK
CK
CK
CK
CK
V
Note
1)2)3)4)5)6)
9)
13)
13)
14)15)
14)16)
1)
13)
13)
17)18)
18)19)
20)
21)
22)
22)
DDQ
is