hyb18t512160afl-3.7 Infineon Technologies Corporation, hyb18t512160afl-3.7 Datasheet - Page 96

• Manufacturer Part Number: hyb18t512160afl-3.7
• Description: 512-mbit Ddr2 Sdram
• Manufacturer: Infineon Technologies Corporation

Table 51
Speed Grade
IFX Sort Name
CAS-RCD-RP latencies
Parameter
Clock Frequency
Row Active Time
Row Cycle Time
RAS-CAS-Delay
Row Precharge Time
1) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a
2) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross. The DQS/DQS,
3) Inputs are not recognized as valid until
4) The output timing reference voltage level is
5)
Data Sheet
differential Slew Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode. For other
Slew Rates see Chapter 8. Timings are further guaranteed for normal OCD drive strength (EMRS(1) A1 = 0) under the
“Reference Load for Timing Measurements” according to Chapter 8.1 only.
RDQS/RDQS, input reference level is the crosspoint when in differential strobe mode; The input reference level for signals
other than CK/CK, DQS/DQS, RDQS/RDQS is defined in Chapter 8.3.
recognized as low.
t
equal to 9 x
RAS.MAX
is calculated from the maximum amount of time a DDR2 device can operate without a refresh command which is
Speed Grade Definition Speed Bins for DDR2–533 and DDR2–400
t
REFI
.
@ CL = 3
@ CL = 4
@ CL = 5
Symbol
t
t
t
t
t
t
t
V
CK
CK
CK
RAS
RC
RCD
RP
REF
V
stabilizes. During the period before
TT
. See section 8 for the reference load for timing measurements.
DDR2–533C
–3.7
4–4–4
Min.
5
3.75
3.75
45
60
15
15
97
HYB18T512[40/80/16]0AF(L)–[3/3S/3.7/5]
Max.
8
8
8
70000
—
—
—
DDR2–400B
–5
3–3–3
Min.
5
5
5
40
55
15
15
V
REF
stabilizes, CKE = 0.2 x
Max.
8
8
8
70000
—
—
—
512-Mbit DDR2 SDRAM
Electrical Characteristics
09112003-SDM9-IQ3P
Unit
t
—
ns
ns
ns
ns
ns
ns
ns
CK
Rev. 1.6, 2005-08
V
Notes
1)2)3)4)
1)2)3)4)
1)2)3)4)
1)2)3)4)5)
1)2)3)4)
1)2)3)4)
1)2)3)4)
DDQ
is