hyb18t512160afl-3.7 Infineon Technologies Corporation, hyb18t512160afl-3.7 Datasheet - Page 11

• Manufacturer Part Number: hyb18t512160afl-3.7
• Description: 512-mbit Ddr2 Sdram
• Manufacturer: Infineon Technologies Corporation

Table 2
Product Type Speed Code
Speed Grade
max. Clock Frequency
min. RAS-CAS-Delay
min. Row Precharge Time
min. Row Active Time
min. Row Cycle Time
1.2
The 512-Mbit DDR2 DRAM is a high-speed Double-
Data-Rate-2 CMOS Synchronous DRAM device
containing 536,870,912 bits and internally configured
as a quad-bank DRAM. The 512-Mbit device is
organized as either 32 Mbit × 4 I/O × 4 banks, 16 Mbit
× 8 I/O × 4 banks or 8 Mbit × 16 I/O × 4 banks chip.
These synchronous devices achieve high speed
transfer rates starting at 400 Mb/sec/pin for general
applications. See
The device is designed to comply with all DDR2 DRAM
key features:
1. posted CAS with additive latency,
2. write latency = read latency - 1,
3. normal and weak strength data-output driver,
4. Off-Chip Driver (OCD) impedance adjustment
5. On-Die Termination (ODT) function.
Data Sheet
High Performance for DDR2–400B and DDR2–533C
Description
Table 3
for performance figures.
@CL5
@CL4
@CL3
f
f
f
t
t
t
t
CK5
CK4
CK3
RCD
RP
RAS
RC
–3.7
DDR2–533 4–4–4
266
266
200
15
15
45
60
12
All of the control and address inputs are synchronized
with a pair of externally supplied differential clocks.
Inputs are latched at the cross point of differential
clocks (CK rising and CK falling). All I/Os are
synchronized with a single ended DQS or differential
DQS-DQS pair in a source synchronous fashion.
A 16-bit address bus for ×4 and ×8 organised
components and a 15-bit address bus for ×16
components is used to convey row, column and bank
address information in a RAS-CAS multiplexing style.
The DDR2 device operates with a 1.8 V
supply. An Auto-Refresh and Self-Refresh mode is
provided along with various power-saving power-down
modes.
The
specifications included in this data sheet are for the
DLL Enabled mode of operation.
The DDR2 SDRAM is available in P-TFBGA-60 and P-
TFBGA-84 package.
HYB18T512[40/80/16]0AF(L)–[3/3S/3.7/5]
functionality
DDR2–400 3–3–3
–5
200
200
200
15
15
40
55
described
512-Mbit DDR2 SDRAM
09112003-SDM9-IQ3P
and
Rev. 1.6, 2005-08
±
the
0.1 V power
Overview
Unit
—
MHz
MHz
MHz
ns
ns
ns
ns
timing