hyb18t512160afl-3.7 Infineon Technologies Corporation, hyb18t512160afl-3.7 Datasheet - Page 16

• Manufacturer Part Number: hyb18t512160afl-3.7
• Description: 512-mbit Ddr2 Sdram
• Manufacturer: Infineon Technologies Corporation

Table 4
Ball#/Pin#
G8
G2
H7
H3
H1
H9
F1
F9
C8
C2
D7
D3
D1
D9
B1
B9
Data Strobe ×4/×8 organisations
B7
A8
Data Strobe ×8 organisations
B3
A2
Data Strobe ×16 organization
B7
A8
F7
E8
Data Mask ×4/×8 organizations
Data Sheet
Pin Configuration of DDR2 SDRAM
Name
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQS
DQS
RDQS
RDQS
UDQS
UDQS
LDQS
LDQS
Pin
Type
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
O
I/O
I/O
I/O
I/O
Buffer
Type
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
Function
Data Signal 15:0
Note: Bi-directional data bus. DQ[15:0] for
Data Strobe
Note: Output with read data, input with write data. Edge aligned
Read Data Strobe
Note: RDQS and RDQS are optional to be enabled by EMRS(1)
Data Strobe Upper Byte
Note: UDQS corresponds to the data on DQ[15:8]
Data Strobe Lower Byte
Note: LDQS corresponds to the data on DQ[7:0]
with read data, centered with write data. LDQS corresponds
to the data on DQ[7:0]; UDQS corresponds to the data on
DQ[15:8]. The datastrobes DQS, LDQS, UDQS may be
used in single ended mode or paired with the optional
complementary signals DQS, LDQS, UDQS to provide
differential pair signaling to the system during both reads
and writes. An EMRS(1) control bit enables or disables the
complementary data strobe signals. For x8 components to
switch from bidirectional to unidirectional is supported and
selected by EMRS(1) control bit.
control bits. see functional description of DM and DQS pins.
Although RDQS/RDQS pins are output only the loading
matches the DQ and DQS loading.
17
HYB18T512[40/80/16]0AF(L)–[3/3S/3.7/5]
Pin Configuration and Block Diagrams
512-Mbit DDR2 SDRAM
×
09112003-SDM9-IQ3P
16 components
Rev. 1.6, 2005-08