hyb18t512160afl-3.7 Infineon Technologies Corporation, hyb18t512160afl-3.7 Datasheet - Page 44

• Manufacturer Part Number: hyb18t512160afl-3.7
• Description: 512-mbit Ddr2 Sdram
• Manufacturer: Infineon Technologies Corporation

3.14
The Bank Activate command is issued by holding CAS
and WE HIGH with CS and RAS LOW at the rising edge
of the clock. The bank addresses BA[1:0] are used to
select the desired bank. The row addresses A0 through
A13 are used to determine which row to activate in the
selected bank for ×4 and ×8 organized components.
For ×16 components row addresses A0 through A12
have to be applied. The Bank Activate command must
be applied before any Read or Write operation can be
executed. Immediately after the bank active command,
the DDR2 SDRAM can accept a read or write command
(with or without Auto-Precharge) on the following clock
cycle. If a R/W command is issued to a bank that has
not satisfied the
Figure 17
t
Data Sheet
RCD
Address
Command
CK, CK
= 3, AL = 2,
Bank Activate Command
Bank Activate Command Cycle
Row Addr.
T0
Activate
Bank A
Bank A
Bank A to Bank B delay tRRD.
t
Internal RAS-CAS delay tRCDmin.
RP
t
RCD.MIN
= 3,
Posted CAS
Col. Addr.
Read A
T1
Bank A
t
RRD
tRAS Row Active Time (Bank A)
specification, then additive
additive latency AL=2
= 2
tCCD
Row Addr.
T2
Activate
Bank B
Bank B
Posted CAS
Col. Addr.
Read B
T3
Bank B
Read A
Begins
45
tRC Row Cycle Time (Bank A)
T4
latency must be programmed into the device to delay
the R/W command which is internally issued to the
device. The additive latency value must be chosen to
assure
3, 4 and 5 are supported. Once a bank has been
activated it must be precharged before another Bank
Activate command can be applied to the same bank.
The bank active and precharge times are defined as
t
between successive Bank Activate commands to the
same bank is determined by
interval between Bank Active commands to different
banks is
RAS
HYB18T512[40/80/16]0AF(L)–[3/3S/3.7/5]
and
t
RCD.MIN
t
Tn
Precharge
t
RRD
RP
Bank A
Bank A
Addr.
, respectively. The minimum time interval
.
is satisfied. Additive latencies of 0, 1, 2,
tRP Row Precharge Time (Bank A)
Tn+1
NOP
NOP
512-Mbit DDR2 SDRAM
Tn+2
Precharge
Functional Description
t
Bank B
Bank B
RC
09112003-SDM9-IQ3P
Addr.
. The minimum time
Rev. 1.6, 2005-08
Tn+3
Row Addr.
Activate
Bank A
Bank A
ACT