hyb18t512160afl-3.7 Infineon Technologies Corporation, hyb18t512160afl-3.7 Datasheet - Page 103

• Manufacturer Part Number: hyb18t512160afl-3.7
• Description: 512-mbit Ddr2 Sdram
• Manufacturer: Infineon Technologies Corporation

7) For each of the terms, if not already an integer, round to the next highest integer.
8) The clock frequency is allowed to change during self-refresh mode or precharge power-down mode. In case of clock
9) For timing definition, Slew Rate and Slew Rate derating see Chapter 8.3
10) For timing definition, Slew Rate and Slew Rate derating see Chapter 8.3
11) Consists of data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers as well as
12) MIN (
13) The
14) The Auto-Refresh command interval has be reduced to 3.9 µs when operating the DDR2 DRAM in a temperature range
15) 0 ≤
16) 85 °C <
17) x4 & x8 (1k page size)
18) The
19) x16 (2k page size), not on 256Mbit component
20) The maximum limit for the
21) Minimum
22) User can choose two different active power-down modes for additional power saving via MRS address bit A12. In “standard
Data Sheet
WR refers to the WR parameter stored in the MR.
frequency change during power-down, a specific procedure is required as describes in Chapter 2.12.
output Slew Rate mis-match between DQS/DQS and associated DQ in any given cycle.
this value can be greater than the minimum specification limits for
no longer driving (
as valid data transitions.These parameters are verified by design and characterization, but not subject to production test.
between 85 °C and 95 °C.
but system performance (bus turnaround) degrades accordingly.
active power-down mode” (MR, A12 = “0”) a fast power-down exit timing
mode” (MR, A12 =”1”) a slow power-down exit timing
T
t
t
CASE
HZ
RRD
t
CL
,
,
T
t
RPST
timing parameter depends on the page size of the DRAM organization. See Chapter 1.5
t
CASE
t
≤ 85 °C
CH
WTR
) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device (i.e.
and
≤ 95 °C
is two clocks when operating the DDR2-SDRAM at frequencies ≤ 200 ΜΗz.
t
t
HZ
LZ
,
,
t
t
RPRE
RPST
t
WPST
), or begins driving (
parameters are referenced to a specific voltage level, which specify when the device output is
parameter is not a device limit. The device operates with a greater value for this parameter,
t
LZ
,
t
RPRE
t
XARDS
).
104
t
HZ
has to be satisfied.
and
HYB18T512[40/80/16]0AF(L)–[3/3S/3.7/5]
t
t
LZ
CL
transitions occur in the same access time windows
and
t
XARD
t
CH
).
can be used. In “low active power-down
t
CK
refers to the application clock period.
512-Mbit DDR2 SDRAM
Electrical Characteristics
09112003-SDM9-IQ3P
Rev. 1.6, 2005-08