hyb18t512160afl-3.7 Infineon Technologies Corporation, hyb18t512160afl-3.7 Datasheet - Page 65

• Manufacturer Part Number: hyb18t512160afl-3.7
• Description: 512-mbit Ddr2 Sdram
• Manufacturer: Infineon Technologies Corporation

3.23.3
The following table summarizes the minimum command delays between Read, Read w/AP, Write, Write w/AP to
the Precharge commands to the same banks and Precharge-All commands.
Table 18
From Command
READ
READ w/AP
WRITE
WRITE w/AP
PRECHARGE
PRECHARGE-ALL PRECHARGE
1) RU{
2) For a given bank, the precharge period should be counted from the latest precharge command, either one bank precharge
Data Sheet
or precharge-all, issued to that bank. The precharge period is satisfied after
command issued to that bank
t
RTP
(ns) /
Read or Write to Precharge Command Spacing Summary
Minimum Command Delays
t
CK
(ns)} must be used, where RU stands for “Round Up”
To Command
PRECHARGE (to same banks as
READ)
PRECHARGE-ALL
PRECHARGE (to same banks as
READ w/AP)
PRECHARGE-ALL
PRECHARGE (to same banks as
WRITE)
PRECHARGE-ALL
PRECHARGE (to same banks as
WRITE w/AP)
PRECHARGE-ALL
PRECHARGE (to same banks as
PRECHARGE)
PRECHARGE-ALL
PRECHARGE-ALL
66
HYB18T512[40/80/16]0AF(L)–[3/3S/3.7/5]
Minimum Delay between “From
Command” to “To Command”
AL + BL/2 + max(
AL + BL/2 + max(
AL + BL/2 + max(
AL + BL/2 + max(
WL + BL/2 +
WL + BL/2 +
WL + BL/2 + WR
WL + BL/2 + WR
1
1
1
1
t
RP,all
t
t
WR
WR
depending on the latest precharge
t
t
t
t
RTP
RTP
RTP
RTP
512-Mbit DDR2 SDRAM
, 2) - 2×
, 2) - 2×
, 2) - 2×
, 2) - 2×
Functional Description
09112003-SDM9-IQ3P
t
t
t
t
CK
CK
CK
CK
Rev. 1.6, 2005-08
Unit
t
t
t
t
t
t
t
t
t
t
t
t
CK
CK
CK
CK
CK
CK
CK
CK
CK
CK
CK
CK
Notes
1)2)
1)2)
1)2)
1)2)
2)
2)
2)
2)
2)
2)
2)
2)