hyb18t512160afl-3.7 Infineon Technologies Corporation, hyb18t512160afl-3.7 Datasheet - Page 21

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hyb18t512160afl-3.7

Manufacturer Part Number
hyb18t512160afl-3.7
Description
512-mbit Ddr2 Sdram
Manufacturer
Infineon Technologies Corporation
Datasheet
Figure 3
Notes
1. UDQS/UDQS is data strobe for DQ[15:8],
Data Sheet
LDQS/LDQS is data strobe for DQ[7:0]
Pin Configuration for ×16 components, PG-TFBGA-84 (top view)
22
2. LDM is the data mask signal for DQ[7:0], UDM is the
3.
HYB18T512[40/80/16]0AF(L)–[3/3S/3.7/5]
data mask signal for DQ[15:8]
V
V
V
DDL
DDL
SSDL
is connected to
and
,
V
SS
V
Pin Configuration and Block Diagrams
, and
SSDL
are power and ground for the DLL.
V
SSQ
V
512-Mbit DDR2 SDRAM
are isolated on the device.
DD
on the device.
09112003-SDM9-IQ3P
Rev. 1.6, 2005-08
V
DD
,
V
DDQ
,

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