x3102v28 Intersil Corporation, x3102v28 Datasheet - Page 16

• Manufacturer Part Number: x3102v28
• Description: 3 Cell Li-ion Battery Protection And Monitor Ic
• Manufacturer: Intersil Corporation

Cell Number Selection
The X3102 is designed to operate with three (3) Li-Ion
battery cells. The CELLN bit of the configuration register
(Table 9) sets the number of cells recognized. For the
X3102, the value for CELLN should always be zero.
The configuration register consists of 16 bits of NOVRAM
memory (Table 2, Table 3). This memory features a high-
speed static RAM (SRAM) overlaid bit-for-bit with non-
volatile “Shadow” EEPROM. An automatic array recall
operation reloads the contents of the shadow EEPROM into
the SRAM configuration register upon power-up (Figure 9).
The configuration register is designed for unlimited write
operations to SRAM, and a minimum of 1,000,000 store
operations to the EEPROM. Data retention is specified to be
greater than 100 years.
It should be noted that the bits of the shadow EEPROM are
for the dedicated use of the configuration register, and are
NOT part of the general purpose 4kbit EEPROM array.
The WCFIG command writes to the configuration register,
see Table 30 and section “X3102 SPI Serial Communication”
on page 27.
After writing to this register using a WCFIG instruction, data
will be stored only in the SRAM of the configuration register.
In order to store data in shadow EEPROM, a WREN
instruction, followed by a EEWRITE to any address of the
4kbit EEPROM memory array must occur, See Figure 10.
This sequence initiates an internal nonvolatile write cycle
which permits data to be stored in the shadow EEPROM
cells. It must be noted that even though a EEWRITE is made
to the general purpose 4kbit EEPROM array, the value and
address to which it is written, is unimportant. If this
procedure is not followed, the configuration register will
power up to the last previously stored values following a
power down sequence.
TABLE 9. SELECTION OF NUMBER OF BATTERY CELLS
FIGURE 9. POWER UP OF CONFIGURATION REGISTER
Configuration Register (SRAM)
Upper Byte
CONFIGURATION
REGISTER BIT
CELLN
1
0
Recall
16
Lower Byte
Not used
3 Li-Ion battery cells
OPERATION
Shadow EEPROM
Recall
X3102
Control Register
The Control Register is realized as two bytes of volatile RAM
(Table 10, Table 11). This register is written using the
WCNTR instruction, see Table 30 and section “X3102 SPI
Serial Communication” on page 27.
Since the control register is volatile, data will be lost
following a power down and power up sequence. The default
value of the control register on initial power up or when
exiting the SLEEP MODE is 00h (for both upper and lower
14
SLP
x
7
FIGURE 10. WRITING TO CONFIGURATION REGISTER
Configuration Register
(SRAM=old value)
TABLE 11. CONTROL REGISTER - LOWER BYTE
TABLE 10. CONTROL REGISTER - UPPER BYTE
Power Down
CBC3
WCFIG (New Value)
Power Up
14
Data Recalled
from Shadow
EEPROM to SRAM
6
0
Data Recalled
from Shadow
EEPROM to SRAM
NO
CBC2
13
5
0
Configuration Register
Configuration Register
(Sram=New Value)
(SRAM=Old Value)
CBC1 UVPC OVPC CSG1 CSG0
12
(New Value)
in Shadow
Power Up
EEPROM
4
x
Store
Data Recalled
from Shadow
EEPROM to SRAM
11
3
x
EEWRITE
Configuration Register
(SRAM=New Value)
WREN
10
4kbit EEPROM
Power Down
2
x
YES
Power Up
Write to
Enable
Write
December 22, 2004
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1
x
FN8246.0
8
0
x