x3102v28 Intersil Corporation, x3102v28 Datasheet - Page 26

• Manufacturer Part Number: x3102v28
• Description: 3 Cell Li-ion Battery Protection And Monitor Ic
• Manufacturer: Intersil Corporation

Voltage Regulator
The X3102 is able to supply peripheral devices with a regulated
5VDC±0.5% output at pin RGO. The voltage regulator should
be configured externally as shown in Figure 16.
The non-inverting input of OP1 is fed with a high precision
5VDC supply. The voltage at the output of the voltage
regulator (V
inverting input of OP1. The output of OP1 in turn drives the
regulator pnp transistor (Q1). The negative feedback at the
regulator output maintains the voltage at 5VDC ±0.5%
(including ripple) despite changes in load, and differences in
regulator transistors.
When power is applied to pin VCC of the X3102, V
regulated to 5VDC±10% for a nominal time of T
During this time period, V
value of 5VDC ±0.5% (Figure 8).
The maximum current that can flow from the voltage
regulator (I
(R
across VCC and RGP reaches a nominal 2.5V (i.e. the
threshold voltage for the FET), Q2 switches ON, shorting VCC
to the base of Q1. Since the base voltage of Q1 is now
higher than the emitter voltage, Q1 switches OFF, and hence
the supply current goes to zero.
Typical values for R
order to protect the voltage regulator circuitry from damage
in case of a short-circuit, R
used.
When choosing the value of R
PNP transistor used should also be taken into consideration.
The transistor should have a gain of at least 100 to support
an output current of 250mA.
LMT
R
10:
25:
50:
LMT
TABLE 27. TYPICAL VALUES FOR R
) connected between RGP and VCC. When the voltage
LMT
RGO
VOLTAGE REGULATOR CURRENT LIMIT (I
) is controlled by the current limiting resistor
) is compared to this 5V reference via the
LMT
and I
RGO
250mA ± 50% (Typical)
100mA ± 50% (Typical)
LMT
50mA ± 50% (Typical)
26
LMT
LMT
is “tuned” to attain a final
t 10:should always be
, the drive limitations of the
are shown in Table 27. In
LMT
AND I
OC
+2ms.
RGO
LMT
LMT
is
)
X3102
4KBit EEPROM Memory
The X3102 contains a CMOS 4k-bit serial EEPROM,
internally organized as 512 x 8 bits. This memory is
accessible via the SPI port, and features the IDLock
function.
The 4kbit EEPROM array can be accessed by the SPI port at
any time, even during a protection mode, except during sleep
mode. After power is applied to VCC of the X3102, EEREAD
and EEWRITE Instructions can be executed only after times
t
time) respectively.
IDLock is a programmable locking mechanism which allows
the user to lock data in different portions of the EEPROM
memory space, ranging from as little as one page to as
much as 1/2 of the total array. This is useful for storing
information such as battery pack serial number,
manufacturing codes, battery cell chemistry data, or cell
characteristics.
EEPROM Write Enable Latch
The X3102 contains an EEPROM “Write Enable” latch. This
latch must be SET before a write to EEPROM operation is
initiated. The WREN instruction will set the latch and the
WRDI instruction will reset the latch (Figure 17). This latch is
automatically reset upon a power-up condition and after the
completion of a byte or page write cycle.
IDLock Memory
Intersil’s IDLock memory provides a flexible mechanism to
store and lock battery cell/pack information. There are seven
distinct IDLock memory areas within the array which vary in
size from one page to as much as half of the entire array.
PUR
Regulating Circuitry
Precision
Reference
Tuning
5VDC
Voltage
To Internal Voltage
(power up to read time) and t
FIGURE 16. VOLTAGE REGULATOR OPERATION
X3102
+
_
OP1
Q2
RGC
RGO
VCC
RGP
PUW
(power up to write
Regulated
5VDC Output
Q1
0.1
µF
December 22, 2004
R
I
Un-Regulated
Voltage
Input
LMT
LMT
V
RGO
FN8246.0