x3102v28 Intersil Corporation, x3102v28 Datasheet - Page 17

• Manufacturer Part Number: x3102v28
• Description: 3 Cell Li-ion Battery Protection And Monitor Ic
• Manufacturer: Intersil Corporation

bytes respectively). The functions that can be manipulated
by the Control Register are shown in Table 12.
Sleep Control (SLP)
Setting the SLP bit to ‘1’ forces the X3102 into the sleep
mode, if V
Current Sense Gain (CSG1, CSG0)
These bits set the gain of the current sense amplifier. These
are x10, x25, x80 and x160. For more detail, see section
“Current Monitor Function” on page 25.
Charge/Discharge Control (OVPC, UVPC)
The OVPC and UVPC bits allow control of cell charge and
discharge externally, via the SPI port. These bits control the
OVP/LMON and UVP/OCP pins, which in turn control the
external power FETs.
Using P-channel power FETs ensures that the FET is on
when the pin voltage is low (Vss), and off when the pin
voltage is high (Vcc).
CONTROL REGISTER BITS
CONTROL REGISTER BITS
BIT(S)
0–4
5, 6
8,9
10
11
12
13
14
15
7
CSG1
TABLE 12. CONTROL REGISTER FUNCTIONALITY
0
0
1
1
TABLE 14. CURRENT SENSE GAIN CONTROL
NAME
CSG1,
OVPC
CSG0
UVPC
CBC1
CBC2
CBC3
CC
SLP
0, 0
–
–
SLP
TABLE 13. SLEEP MODE SELECTION
0
1
< V
SLP
OVP control: switch pin OVP = V
CSG0
(don’t care)
Reserved—write 0 to these locations.
Select sleep mode.
Select current sense voltage gain
UVP control: switch pin UVP = V
CB1 control: switch pin CB1 = V
CB2 control: switch pin CB2 = V
CB3 control: switch pin CB3 = V
(don’t care)
0
1
0
1
. See section “Sleep Mode” on page 20.
Set current sense gain=x10
Set current sense gain=x25
Set current sense gain=x80
Set current sense gain=x160
Normal operation mode
Device enters Sleep mode
17
FUNCTION
OPERATION
OPERATION
CC
CC
CC
CC
CC
/V
/V
/V
/V
/V
SS
SS
SS
SS
SS
X3102
OVP/LMON and UVP/OCP can be controlled by using the
WCNTR Instruction to set bits OVPC and UVPC in the
Control register (See page 17).
It is possible to set/change the values of OVPC and UVPC
during a protection mode. A change in the state of the pins
OVP/LMON and UVP/OCP, however, will not take place until
the device has returned from the protection mode.
Cell Voltage Balance Control (CBC1–CBC3)
This function can be used to adjust individual battery cell
voltage during charging. Pins CB1–CB3 are used to control
external power switching devices. Cell voltage balancing is
achieved via the SPI port.
CB1–CB3 can be controlled by using the WCNTR Instruction
to set bits CBC1–CBC3 in the control register (Table 16).
Status Register
The status of the X3102 can be verified by using the
RDSTAT command to read the contents of the Status
Register (Table 17).
7
0
CBC3
CONTROL REGISTER
OVPC
1
0
x
x
x
x
x
x
Control Register Bits
1
0
x
x
6
0
BITS
5
0
CBC2
TABLE 16. CB1–CB3 CONTROL
TABLE 15. UVP/OVP CONTROL
x
x
1
0
x
x
x
x
TABLE 17. STATUS REGISTER
UVPC
4
0
x
x
1
0
3
0
CBC1
1
0
x
x
x
x
x
x
Pin OVP = V
Pin OVP = V
Pin UVP = V
Pin UVP = V
CCES +
OVDS
2
Set CB1 = V
Set CB1 = V
Set CB2 = V
Set CB2 = V
Set CB3 = V
Set CB3 = V
Set CB4 = V
Set CB4 = V
OPERATION
SS
CC
SS
CC
UVDS
Operation
(FET ON)
(FET ON)
(FET OFF)
(FET OFF)
1
CC
SS
CC
SS
CC
SS
CC
SS
(OFF)
(OFF)
(OFF)
(OFF)
(ON)
(ON)
(ON)
(ON)
December 22, 2004
VRGS +
OCDS
0
FN8246.0