x3102v28 Intersil Corporation, x3102v28 Datasheet - Page 22

• Manufacturer Part Number: x3102v28
• Description: 3 Cell Li-ion Battery Protection And Monitor Ic
• Manufacturer: Intersil Corporation

EVENT
(1,2)
(2,3)
(3,4)
(4,5)
[0,1)
[1]
[2]
[3]
[4]
[5]
• Charge FET is ON (OVP/LMON = V
• Discharge FET is ON (UVP/OCP = V
• All cell voltages (VCELL
• The device is in normal operation mode (i.e. not in a protection mode).
• The voltage of one or more of the battery cells (V
• The internal over-discharge detection delay timer begins counting down.
• The device is still in normal operation mode
• The internal over-discharge detection delay timer continues counting for T
• The internal over-discharge detection delay timer times out, AND V
• The internal over-discharge sense circuitry switches the discharge FET OFF (UVP/OCP = Vcc).
• The charge FET is switched OFF (OVP/LMON = V
• The device has now entered over-discharge protection mode.
• At the same time, the device enters sleep mode (See section “Voltage Regulator” on page 26).
• While device is in sleep (in over-discharge protection) mode:
• The power to ALL internal circuits is switched OFF limiting power consumption to less than 1µA.
• The output of the 5VDC voltage regulator (RGO) is 0V.
• Access to the X3102 via the SPI port is NOT possible.
• Return from sleep mode (but still in over-discharge protection mode):
• Vcc rises above the “Return from Sleep mode threshold Voltage” (V
• Power is returned to ALL internal circuitry
• 5VDC output is returned to the regulator output (RGO).
• Access is enabled to the X3102 via the SPI port.
• The status of the discharge FET remains OFF (It is possible to change the status of UVPC in the control register, although it will
If the cell charge enable function is
switched ON
AND V
OR
Charge enable function is
switched OFF
If the cell charge enable function is
switched ON
AND
V
• The voltage of all of the battery cells (V
• The internal Over-discharge release timer begins counting down.
• The X3102 is still in over-discharge protection mode.
• The internal over-discharge release timer continues counting for t
• The X3102 should be in monitor mode (AS2:AS0 not all low) for recovery time based on t
• The internal over-discharge release timer times out, AND V
• The device returns from over-discharge protection mode, and is now in normal operation mode.
• The Charger voltage can now drop below VSLR and the
• The discharge FET is can now be switched ON (UVP/OCP = V
• The status of the charge FET remains unaffected (ON)
• The battery cells continue to receive charge via the charge FET and discharge FET (both ON).
CELL
pack was connected to a charger. The X3102 is now powered via P+/P-, and not the battery pack cells.
have no effect at this time).
successive samples about 120ms apart.
control register.
CELL
< V
CE
> V
TABLE 22. OVER-DISCHARGE PROTECTION MODE—EVENT DIAGRAM DESCRIPTION
CE
22
1
–VCELL
• The X3102 initiates a reset operation that takes the longer of T
• The charge FET is switched On (OVP/LMON = Vss) by the microcontroller by writing a “1” to
• The battery cells now receive charge via the charge FET and diode D1 across the discharge
• The X3102 monitors the V
• Charge/discharge of the battery cells via P+ is no longer permitted (Charge FET and discharge
• (Charging may re-commence only when the Cell Charge Enable function is switched OFF -
4
) are above the Over-discharge threshold voltage (V
complete. Do not write to the FET control bits during this time.
the OVPC bit in the control register.
FET (which is OFF).
FET are held OFF).
See Sections: “Configuration Register” page 4, and “Sleep mode” page 17.)
SS
SS
)
CELL
), and hence battery cells are permitted to discharge.
), have risen above V
CELL
CC
EVENT DESCRIPTION
X3102
).
), falls below V
X3102
CELL
CELL
SS
is still above V
UVR
UVR
will not go back to sleep.
) by the microcontroller by writing a “1” to the UVPC bit of the
CELL
SLR
voltage to determine whether or not it has risen above V
UV
.
seconds.
.
)—This would normally occur in the case that the battery
is still below V
UV
seconds.
UVR.
UV
UV.
UVR
).
. Otherwise recovery is based on two
OV
+200ms or T
UV
December 22, 2004
+200ms to
FN8246.0
UVR
.