x3102v28 Intersil Corporation, x3102v28 Datasheet - Page 21

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x3102v28

Manufacturer Part Number
x3102v28
Description
3 Cell Li-ion Battery Protection And Monitor Ic
Manufacturer
Intersil Corporation
Datasheet
UVP/OCP and OVP/LMON via bits UVPC and OVPC in the
control register is also prohibited.
The device returns from sleep mode when V
when the battery terminals are connected to a battery
charger). In this case, the X3102 restores the 5VDC
regulated output (section “Voltage Regulator” on page 26),
and communication via the SPI port resumes.
If the Cell Charge Enable function is enabled when V
rises above V
individual battery cell voltages (V
cell charge enable voltage (V
be turned on. The value of V
WCFIG command to set bits VCE1–VCE0 in the
configuration register.
Only if the condition “
the state of
control register
NOTES:
1.
2. OVP/LMON stays high until the microcontroller writes a “1” to the OVPC bit in the control register. This sets the signal low, which turns on the charge FET. It cannot be turned
3. UVP/OCP stays high until the microcontroller writes a “1” to the UVPC bit in the control register. This sets the signal low, which turns on the discharge FET. The FET cannot
If SWEN=0 and V
on prior to this time.
be turned on prior to this time.
UVP/OCP
OVP/LMON
RGO
V
VCELL
V
CC
UV
Event
charge and discharge FETs be changed via the
SLR
.
Otherwise, if V
CELL
, the X3102 internally verifies that the
0
< V
CE
V
, then OVP/LMON stays high and charging is prohibited.
CELL
CE
21
CE
FIGURE 12. OVER-DISCHARGE PROTECTION MODE-EVENT DIAGRAM
CELL
) before allowing the FETs to
is selected by using the
>
CELL
V
CE
1
<
) are larger than the
” is satisfied can
V
T
UV
CE
CC
for any battery
The Longer of TOV+200ms OR TUV+200ms
tV
2
SLR
CC
. (e.g.
Over-discharge Protection Mode
Sleep Mode
X3102
0.7V
cell then both the Charge FET and the discharge FET are OFF
(OVP/LMON = V
and discharge of the battery cells via terminals P+ / P- is
prohibited (See Note).
NOTE: In this case, charging of the battery may resume ONLY if the
cell charge enable function is switched OFF by setting bit SWCEN=1
in the configuration register (See Above, “CONFIGURATION
REGISTER FUNCTIONALITY” on page 15).
The cell charging threshold function can be switched ON or
OFF by the user, by setting bit SWCEN in the configuration
register (Table 7) using the WCFIG command. In the case
that this cell charge enable function is switched OFF, then
V
The X3102 cannot enter sleep mode (automatically or
manually, by setting the SLP bit) if V
ensure that the device does not go into a sleep mode while
the battery cells are at a high voltage (e.g. during cell
charging).
CE
is effectively set to 0V.
Notes 1, 2
3
Cell Charge Prohibited if SWCEN=0
CC
AND V
and UVP/OCP = V
4
CELL
T
UVR
< V
CE
5
CC
Note 3
CC
tV
). Thus both charge
SLR
December 22, 2004
. This is to
V
V
V
V
V
V
V
5V
0V
SLR
UVR
CE
CC
SS
CC
SS
FN8246.0

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