x3102v28 Intersil Corporation, x3102v28 Datasheet - Page 27

• Manufacturer Part Number: x3102v28
• Description: 3 Cell Li-ion Battery Protection And Monitor Ic
• Manufacturer: Intersil Corporation

Prior to any attempt to perform an IDLock operation, the
WREN instruction must first be issued. This instruction sets
the “Write Enable” latch and allows the part to respond to an
IDLock sequence. The EEPROM memory may then be
IDLocked by writing the
Figure 25), followed by the IDLock protection byte.
The IDLock protection byte contains the IDLock bits IDL2-
IDL0, which defines the particular partition to be locked
(Table 28). The rest of the bits [7:3] are unused and must be
written as zeroes. Bringing CS HIGH after the two byte
IDLock instruction initiates a nonvolatile write to the status
register. Writing more than one byte to the status register will
overwrite the previously written IDLock byte.
Once an IDLock instruction has been completed, that IDLock
setup is held in a nonvolatile IDLock Register (Table 29) until
the next IDLock instruction is issued. The sections of the
*Instructions have the MSB in leftmost position and are transferred MSB first.
IDLock PROTECTION
INSTRUCTION
EEREAD STAT
EEWRITE
EEREAD
RDSTAT
WCNTR
SET IDL
TABLE 28. IDLock PARTITION BYTE DEFINITION
WCFIG
NAME
WREN
WRDI
0000 0000
0000 0001
0000 0010
0000 0011
0000 0100
0000 0101
0000 0110
0000 0111
BYTES
INSTRUCTION
SET IDL
0000 0100
0000 0010
0000 0101
0000 1001
0000 1010
FORMAT*
0000 0110
0000 0011
0000 1011
0000 0001
EEPROM MEMORY ADDRESS
27
instruction (Table 30 and
1F0h–1FFh
000h–07Fh
080h–0FFh
100h–17Fh
180h–1FFh
000h–0FFh
000h–00Fh
IDLocked
Set the write enable latch (write enable operation) (Figure 17)
Reset the write enable latch (write disable operation) (Figure 17)
Write command followed by address/data (4kbit EEPROM) (Figure 18, Figure 19)
Reads IDLock settings & status of EEPROM EEWRITE instruction (Figure 20)
Read operation followed by address (for 4kbit EEPROM) (Figure 21)
Write to configuration register followed by two bytes of data (Figure 10, Figure 22). Data stored in
SRAM only and will power-up to previous settings (Figure 9)
Write to control register, followed by two bytes of data (Figure 23)
Read contents of status register (Figure 24)
Set EEPROM ID lock partition followed by partition byte (Figure 25)
None
TABLE 30. INSTRUCTION SET
X3102
memory array that are IDLocked can be read but not written
until IDLock is removed or changed.
NOTE: Bits [7:3] specified to be “0’s”.
X3102 SPI Serial Communication
The X3102 is designed to interface directly with the
synchronous Serial Peripheral Interface (SPI) of many
popular microcontroller families. This interface uses four
signals, CS, SCK, SI and SO. The signal CS when low,
enables communications with the device. The SI pin carries
the input signal and SO provides the output signal. SCK
clocks data in or out. The X3102 operates in SPI mode 0
which requires SCK to be normally low when not transferring
data. It also specifies that the rising edge of SCK clocks data
into the device, while the falling edge of SCK clocks data out.
This SPI port is used to set the various internal registers,
write to the EEPROM array, and select various device
functions.
The X3102 contains an 8-bit instruction register. It is
accessed by clocking data into the SI input. CS must be
LOW during the entire operation. Table 30 contains a list of
the instructions and their opcodes. All instructions,
addresses and data are transferred MSB first.
Data input is sampled on the first rising edge of SCK after
CS goes LOW. SCK is static, allowing the user to stop the
clock, and then start it again to resume operations where
left off.
7
0
DESCRIPTION
6
0
TABLE 29. IDLock REGISTER
5
0
4
0
3
0
IDL2
2
IDL1
December 22, 2004
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FN8246.0
IDL0
0