tmp86c847iug TOSHIBA Semiconductor CORPORATION, tmp86c847iug Datasheet - Page 119

• Manufacturer Part Number: tmp86c847iug
• Description: 8 Bit Microcontroller
• Manufacturer: TOSHIBA Semiconductor CORPORATION

SIOCR1<SIOS>
SIOSR<SIOF>
SIOSR<SEF>
SCK
SI pin
SIOSR<RXF>
INTSIO
interrupt
request
SIORDB
pin
Figure 10-10 Example of Internal Clock and MSB Receive Mode
(3)
tion is finished. Then INTSIO interrupt request is generated after SIOSR<RXERR> is set to “1”.
If received data is not read out from SIORDB receive error occurs immediately after shift opera-
Stopping the receive operation
There are two ways for stopping the receive operation.
A7
• The way of clearing SIOCR1<SIOS>.
• The way of setting SIOCR1<SIOINH>.
A6 A5 A4 A3 A2 A1
When SIOCR1<SIOS> is cleared to “0”, receive operation is stopped after all of the data is
finished to receive. When receive operation is finished, SIOSR<SIOF> is cleared to “0”.
In external clock operation, SIOCR1<SIOS> must be cleared to “0” before SIOSR<SEF> is
set to “1” by starting the next shift operation.
Receive operation is stopped immediately after SIOCR1<SIOINH> is set to “1”. In this case,
SIOCR1<SIOS>, SIOSR register, SIORDB register and SIOTDB register are initialized.
Start shift
operation
Automatic wait
A0
A
Reading received
data A
Page 111
B7 B6 B5 B4 B3 B2 B1
Start shift
operation
Reading received
data B
B0
B
C7
Start shift
operation
C6 C5 C4 C3 C2 C1 C0
Clearing SIOS
Reading received
data C
TMP86C847IUG
C