tmp86c847iug TOSHIBA Semiconductor CORPORATION, tmp86c847iug Datasheet - Page 24

• Manufacturer Part Number: tmp86c847iug
• Description: 8 Bit Microcontroller
• Manufacturer: TOSHIBA Semiconductor CORPORATION

2.2 System Clock Controller
2. Operational Description
2.2.4 Operating Mode Control
2.2.4.1
Example 1 :Starting STOP mode from NORMAL mode by testing a port P20.
Note 8: Before setting TGHALT to “1”, be sure to stop peripherals. If peripherals are not stopped, the interrupt latch of peripherals
SSTOPH:
may be set after IDLE0 or SLEEP0 mode is released.
(STOP5 to STOP2) which are controlled by the STOP mode release control register (STOPCR).
The
started by setting SYSCR1<STOP> to “1”. During STOP mode, the following status is maintained.
selected with the SYSCR1<RELM>. Do not use any key-on wakeup input (STOP5 to STOP2) for releas-
ing STOP mode in edge-sensitive mode.
STOP mode
(1)
STOP mode is controlled by the system control register 1, the
STOP mode includes a level-sensitive mode and an edge-sensitive mode, either of which can be
Note 1: The STOP mode can be released by either the STOP or key-on wakeup pins (STOP5 to STOP2).
Note 2: During STOP period (from start of STOP mode to end of warm up), due to changes in the external
STOP
the STOP5 to STOP2 pins which are enabled by STOPCR. This mode is used for capacitor backup
when the main power supply is cut off and long term battery backup.
to STOP2 inputs are low, STOP mode does not start but instead the warm-up sequence starts imme-
diately. Thus, to start STOP mode in the level-sensitive release mode, it is necessary for the program
to first confirm that the
ing two methods can be used for confirmation.
1. Oscillations are turned off, and all internal operations are halted.
2. The data memory, registers, the program status word and port output latches are all held in the
3. The prescaler and the divider of the timing generator are cleared to “0”.
4. The program counter holds the address 2 ahead of the instruction (e.g., [SET (SYSCR1).7])
Level-sensitive release mode (RELM = “1”)
In this mode, STOP mode is released by setting the
Even if an instruction for starting STOP mode is executed while
LD
TEST
JRS
DI
SET
status in effect before STOP mode was entered.
which started STOP mode.
However, because the STOP pin is different from the key-on wakeup and can not inhibit the release
input, the STOP pin must be used for releasing STOP mode.
interrupt pin signal, interrupt latches may be set to “1” and interrupts may be accepted immediately
after STOP mode is released. Before starting STOP mode, therefore, disable interrupts. Also, before
enabling interrupts after STOP mode is released, clear unnecessary interrupt latches.
1. Testing a port.
2. Using an external interrupt input
pin is also used both as a port P20 and an
(SYSCR1), 01010000B
(P2PRD). 0
F, SSTOPH
(SYSCR1). 7
STOP
pin input is low and the STOP5 to STOP2 inputs are high. The follow-
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; Sets up the level-sensitive release mode
; Wait until the
; IMF ← 0
; Starts STOP mode
INT5
(
INT5
INT5
STOP
pin input goes low level
(external interrupt input 5) pin. STOP mode is
STOP
is a falling edge-sensitive input).
STOP
pin high or detecting low level input for
pin input and key-on wakeup input
STOP
pin input is high or STOP5
TMP86C847IUG