tmp86c847iug TOSHIBA Semiconductor CORPORATION, tmp86c847iug Datasheet - Page 97
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tmp86c847iug
Manufacturer Part Number
tmp86c847iug
Description
8 Bit Microcontroller
Manufacturer
TOSHIBA Semiconductor CORPORATION
Datasheet
1.TMP86C847IUG.pdf
(160 pages)
- Current page: 97 of 160
- Download datasheet (2Mb)
Example :Generating 1024 Hz pulse using TC4 (fc = 16.0 MHz)
Note 1: In the programmable divider output mode, do not change the TTREGj setting while the timer is running.
Note 2: When the timer is stopped during PDO output, the
Note 3: j = 3, 4
Since TTREGj is not in the shift register configuration in the programmable divider output mode, the new
value programmed in TTREGj is in effect immediately after programming. Therefore, if TTREGi is changed
while the timer is running, an expected operation may not be obtained.
stopped. To change the output status, program TCjCR<TFFj> after the timer is stopped. Do not change the
TCjCR<TFFj> setting upon stopping of the timer.
Example: Fixing the
CLR (TCjCR).3: Stops the timer.
CLR (TCjCR).7: Sets the
LD
LD
LD
Setting port
(TTREG4), 3DH
(TC4CR), 00010001B
(TC4CR), 00011001B
PDOj
pin to the high level when the TimerCounter is stopped
PDOj
pin to the high level.
Page 89
: 1/1024
: Sets the operating clock to fc/2
: Starts TC4.
PDOj
pin holds the output status when the timer is
÷
2
7
/fc
÷
2 = 3DH
7
, and 8-bit PDO mode.
TMP86C847IUG
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