attiny13-20ss ATMEL Corporation, attiny13-20ss Datasheet - Page 14

• Manufacturer Part Number: attiny13-20ss
• Description: 8-bit Microcontroller With 1k Bytes In-system Programmable Flash - Atmel Corporation
• Manufacturer: ATMEL Corporation

SRAM Data Memory
Data Memory Access Times
14
ATtiny13
Figure 9 shows how the ATtiny13 SRAM Memory is organized.
The lower 160 Data memory locations address both the Register File, the I/O memory
and the internal data SRAM. The first 32 locations address the Register File, the next 64
locations the standard I/O memory, and the last 64 locations address the internal data
SRAM.
The five different addressing modes for the Data memory cover: Direct, Indirect with
Displacement, Indirect, Indirect with Pre-decrement, and Indirect with Post-increment. In
the Register File, registers R26 to R31 feature the indirect addressing pointer registers.
The direct addressing reaches the entire data space.
The Indirect with Displacement mode reaches 63 address locations from the base
address given by the Y- or Z-register.
When using register indirect addressing modes with automatic pre-decrement and post-
increment, the address registers X, Y, and Z are decremented or incremented.
The 32 general purpose working registers, 64 I/O Registers, and the 64 bytes of internal
data SRAM in the ATtiny13 are all accessible through all these addressing modes. The
Register File is described in “General Purpose Register File” on page 8.
Figure 9. Data Memory Map
This section describes the general access timing concepts for internal memory access.
The internal data SRAM access is performed in two clk
10.
Figure 10. On-chip Data SRAM Access Cycles
Address
clk
Data
Data
WR
CPU
RD
Compute Address
64 I/O Registers
Data Memory
Internal SRAM
32 Registers
T1
Memory Access Instruction
(64 x 8)
Address valid
0x009F
0x0000 - 0x001F
0x0020 - 0x005F
0x0060
T2
CPU
cycles as described in Figure
Next Instruction
T3
2535G–AVR–01/07